ACPI Specification 6.4 Errata A

Acknowledgments

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• List of Tables
• List of Figures
• Revision History
• Overview

• 1. Introduction
  • 1.1. Principal Goals
    • 1.1.1. Principle of Inclusive Terminology
  • 1.2. Power Management Rationale
  • 1.3. Legacy Support
  • 1.4. OEM Implementation Strategy
  • 1.5. Power and Sleep Buttons
  • 1.6. ACPI Specification and the Structure of ACPI
  • 1.7. OS and Platform Compliance
    • 1.7.1. Platform Implementations of ACPI-defined Interfaces
      • 1.7.1.1. Recommended Features and Interface Descriptions for Design Guides
      • 1.7.1.2. Terminology Examples for Design Guides
    • 1.7.2. OSPM Implementations
    • 1.7.3. OS Requirements
  • 1.8. Target Audience
  • 1.9. Document Organization
    • 1.9.1. ACPI Introduction and Overview
    • 1.9.2. Programming Models
    • 1.9.3. Implementation Details
    • 1.9.4. Technical Reference
    • 1.9.5. Revsion Numbers
  • 1.10. Related Documents
• 2. Definition of Terms
  • 2.1. General ACPI Terminology
  • 2.2. Global System State Definitions
  • 2.3. Device Power State Definitions
    • 2.3.1. Device Performance States
  • 2.4. Sleeping and Soft-off State Definitions
  • 2.5. Processor Power State Definitions
  • 2.6. Device and Processor Performance State Definitions
• 3. ACPI Concepts
  • 3.1. System Power Management
  • 3.2. Power States
    • 3.2.1. Power Button
    • 3.2.2. Platform Power Management Characteristics
      • 3.2.2.1. Mobile PC
      • 3.2.2.2. Desktop PCs
      • 3.2.2.3. Multiprocessor and Server PCs
  • 3.3. Device Power Management
    • 3.3.1. Device Power Management Model
    • 3.3.2. Power Management Standards
    • 3.3.3. Device Power States
    • 3.3.4. Device Power State Definitions
  • 3.4. Controlling Device Power
    • 3.4.1. Getting Device Power Capabilities
    • 3.4.2. Setting Device Power States
    • 3.4.3. Getting Device Power Status
    • 3.4.4. Waking the System
    • 3.4.5. Example: Modem Device Power Management
      • 3.4.5.1. Obtaining the Modem Capabilities
      • 3.4.5.2. Setting the Modem Power State
      • 3.4.5.3. Obtaining the Modem Power Status
      • 3.4.5.4. Waking the System
  • 3.5. Processor Power Management
  • 3.6. Device and Processor Performance States
  • 3.7. Configuration and “Plug and Play”
    • 3.7.1. Device Configuration Example: Configuring the Modem
    • 3.7.2. NUMA Nodes
  • 3.8. System Events
  • 3.9. Battery Management
    • 3.9.1. Battery Communications
    • 3.9.2. Battery Capacity
    • 3.9.3. Battery Gas Gauge
    • 3.9.4. Low Battery Levels
      • 3.9.4.1. Emergency Shutdown
    • 3.9.5. Battery Calibration
    • 3.9.6. Battery Charge Limiting
  • 3.10. Thermal Management Concepts
    • 3.10.1. Active and Passive Cooling Modes
    • 3.10.2. Performance vs. Energy Conservation
    • 3.10.3. Acoustics (Noise)
    • 3.10.4. Multiple Thermal Zones
  • 3.11. Flexible Platform Architecture Support
    • 3.11.1. Hardware-reduced ACPI
      • 3.11.1.1. Interrupt-based Wake Events
    • 3.11.2. Low-Power Idle
      • 3.11.2.1. Low Power S0 Idle Capable Flag
    • 3.11.3. Connection Resources
      • 3.11.3.1. Supported Platforms
• 4. ACPI Hardware Specification
  • 4.1. Hardware-Reduced ACPI
    • 4.1.1. Hardware-Reduced Events
      • 4.1.1.1. GPIO-Signaled Events or Interrupt Signaled Events
      • 4.1.1.2. Interrupt-based Wake Events
  • 4.2. Fixed Hardware Programming Model
  • 4.3. Generic Hardware Programming Model
  • 4.4. Diagram Legend
  • 4.5. Register Bit Notation
  • 4.6. The ACPI Hardware Model
    • 4.6.1. Hardware Reserved Bits
    • 4.6.2. Hardware Ignored Bits
    • 4.6.3. Hardware Write-Only Bits
    • 4.6.4. Cross Device Dependencies
      • 4.6.4.1. Example 1: Related Device Interference
      • 4.6.4.2. Example 2: Unrelated Device Interference
  • 4.7. ACPI Hardware Features
  • 4.8. ACPI Register Model
    • 4.8.1. ACPI Register Summary
      • 4.8.1.1. PM1 Event Registers
      • 4.8.1.2. PM1 Control Registers
      • 4.8.1.3. PM2 Control Register
      • 4.8.1.4. PM Timer Register
      • 4.8.1.5. Processor Control Block (P_BLK)
      • 4.8.1.6. General-Purpose Event Registers
    • 4.8.2. Fixed Hardware Features
      • 4.8.2.1. Power Management Timer
      • 4.8.2.2. Console Buttons
      • 4.8.2.3. Sleeping/Wake Control
      • 4.8.2.4. Real Time Clock Alarm
      • 4.8.2.5. Legacy/ACPI Select and the SCI Interrupt
      • 4.8.2.6. Processor Control
    • 4.8.3. Fixed Hardware Registers
      • 4.8.3.1. PM1 Event Grouping
      • 4.8.3.2. PM1 Control Grouping
      • 4.8.3.3. Power Management Timer (PM_TMR)
      • 4.8.3.4. PM2 Control (PM2_CNT)
      • 4.8.3.5. Processor Register Block (P_BLK)
      • 4.8.3.6. Reset Register
      • 4.8.3.7. Sleep Control and Status Registers
    • 4.8.4. Generic Hardware Registers
      • 4.8.4.1. General-Purpose Event Register Blocks
      • 4.8.4.2. Example Generic Devices
• 5. ACPI Software Programming Model
  • 5.1. Overview of the System Description Table Architecture
    • 5.1.1. Address Space Translation
  • 5.2. ACPI System Description Tables
    • 5.2.1. Reserved Bits and Fields
      • 5.2.1.1. Reserved Bits and Software Components
      • 5.2.1.2. Reserved Values and Software Components
      • 5.2.1.3. Reserved Hardware Bits and Software Components
      • 5.2.1.4. Ignored Hardware Bits and Software Components
    • 5.2.2. Compatibility
    • 5.2.3. Address Format
      • 5.2.3.1. Functional Fixed Hardware
      • 5.2.3.2. Generic Address Structure
    • 5.2.4. Universally Unique Identifiers (UUIDs)
    • 5.2.5. Root System Description Pointer (RSDP)
      • 5.2.5.1. Finding the RSDP on IA-PC Systems
      • 5.2.5.2. Finding the RSDP on UEFI Enabled Systems
      • 5.2.5.3. Root System Description Pointer (RSDP) Structure
    • 5.2.6. System Description Table Header
    • 5.2.7. Root System Description Table (RSDT)
    • 5.2.8. Extended System Description Table (XSDT)
    • 5.2.9. Fixed ACPI Description Table (FADT)
      • 5.2.9.1. Preferred PM Profile System Types
      • 5.2.9.2. System Type Attributes
      • 5.2.9.3. IA-PC Boot Architecture Flags
      • 5.2.9.4. ARM Architecture Boot Flags
    • 5.2.10. Firmware ACPI Control Structure (FACS)
      • 5.2.10.1. Global Lock
    • 5.2.11. Definition Blocks
      • 5.2.11.1. Differentiated System Description Table (DSDT)
      • 5.2.11.2. Secondary System Description Table (SSDT)
      • 5.2.11.3. Persistent System Description Table (PSDT)
    • 5.2.12. Multiple APIC Description Table (MADT)
      • 5.2.12.1. MADT Processor Local APIC / SAPIC Structure Entry Order
      • 5.2.12.2. Processor Local APIC Structure
      • 5.2.12.3. I/O APIC Structure
      • 5.2.12.4. Platforms with APIC and Dual 8259 Support
      • 5.2.12.5. Interrupt Source Override Structure
      • 5.2.12.6. Non-Maskable Interrupt (NMI) Source Structure
      • 5.2.12.7. Local APIC NMI Structure
      • 5.2.12.8. Local APIC Address Override Structure
      • 5.2.12.9. I/O SAPIC Structure
      • 5.2.12.10. Local SAPIC Structure
      • 5.2.12.11. Platform Interrupt Source Structure
      • 5.2.12.12. Processor Local x2APIC Structure
      • 5.2.12.13. Local x2APIC NMI Structure
      • 5.2.12.14. GIC CPU Interface (GICC) Structure
      • 5.2.12.15. GIC Distributor (GICD) Structure
      • 5.2.12.16. GIC MSI Frame Structure
      • 5.2.12.17. GIC Redistributor (GICR) Structure
      • 5.2.12.18. GIC Interrupt Translation Service (ITS) Structure
      • 5.2.12.19. Multiprocessor Wakeup Structure
    • 5.2.13. Global System Interrupts
    • 5.2.14. Smart Battery Table (SBST)
    • 5.2.15. Embedded Controller Boot Resources Table (ECDT)
    • 5.2.16. System Resource Affinity Table (SRAT)
      • 5.2.16.1. Processor Local APIC/SAPIC Affinity Structure
      • 5.2.16.2. Memory Affinity Structure
      • 5.2.16.3. Processor Local x2APIC Affinity Structure
      • 5.2.16.4. GICC Affinity Structure
      • 5.2.16.5. GIC Interrupt Translation Service (ITS) Affinity Structure
      • 5.2.16.6. Generic Initiator Affinity Structure
    • 5.2.17. System Locality Information Table (SLIT)
    • 5.2.18. Corrected Platform Error Polling Table (CPEP)
      • 5.2.18.1. Corrected Platform Error Polling Processor Structure
    • 5.2.19. Maximum System Characteristics Table (MSCT)
      • 5.2.19.1. Maximum Proximity Domain Information Structure
    • 5.2.20. ACPI RAS Feature Table (RASF)
      • 5.2.20.1. RASF PCC Sub Channel Identifier
      • 5.2.20.2. Using PCC registers
      • 5.2.20.3. RASF Communication Channel
      • 5.2.20.4. Platform RAS Capabilities
      • 5.2.20.5. Parameter Block
    • 5.2.21. Memory Power State Table (MPST)
      • 5.2.21.1. MPST PCC Sub Channel
      • 5.2.21.2. Memory Power State
      • 5.2.21.3. Action Sequence
      • 5.2.21.4. Memory Power Node
      • 5.2.21.5. Memory Power State Structure
      • 5.2.21.6. Memory Power State Characteristics structure
      • 5.2.21.7. Autonomous Memory Power Management
      • 5.2.21.8. Handling BIOS Reserved Memory
      • 5.2.21.9. Interaction with NUMA processor and memory affinity tables
      • 5.2.21.10. Interaction with Memory Hot Plug
      • 5.2.21.11. OS Memory Allocation Considerations
      • 5.2.21.12. Platform Memory Topology Table (PMTT)
    • 5.2.22. Boot Graphics Resource Table (BGRT)
      • 5.2.22.1. Version
      • 5.2.22.2. Status
      • 5.2.22.3. Image Type
      • 5.2.22.4. Image Address
      • 5.2.22.5. Image Offset
    • 5.2.23. Firmware Performance Data Table (FPDT)
      • 5.2.23.1. Performance Record Format
      • 5.2.23.2. FPDT Performance Record Types
      • 5.2.23.3. Runtime Performance Record Types
      • 5.2.23.4. Firmware Basic Boot Performance Table Pointer Record
      • 5.2.23.5. S3 Performance Table Pointer Record
      • 5.2.23.6. Firmware Basic Boot Performance Table
      • 5.2.23.7. Firmware Basic Boot Performance Data Record
      • 5.2.23.8. S3 Performance Table
    • 5.2.24. Generic Timer Description Table (GTDT)
      • 5.2.24.1. GT Block Structure
      • 5.2.24.2. Arm Generic Watchdog Structure
    • 5.2.25. NVDIMM Firmware Interface Table (NFIT)
      • 5.2.25.1. Overview
      • 5.2.25.2. System Physical Address (SPA) Range Structure
      • 5.2.25.3. NVDIMM Region Mapping Structure
      • 5.2.25.4. Interleave Structure
      • 5.2.25.5. SMBIOS Management Information Structure
      • 5.2.25.6. NVDIMM Control Region Structure
      • 5.2.25.7. NVDIMM Block Data Window Region Structure
      • 5.2.25.8. Flush Hint Address Structure
      • 5.2.25.9. Platform Capabilities Structure
      • 5.2.25.10. NVDIMM Representation Format
    • 5.2.26. Secure Devices (SDEV) ACPI Table
      • 5.2.26.1. Secure Device Structures
    • 5.2.27. Heterogeneous Memory Attribute Table (HMAT)
      • 5.2.27.1. HMAT Overview
      • 5.2.27.2. Memory Side Cache Overview
      • 5.2.27.3. Memory Proximity Domain Attributes Structure
      • 5.2.27.4. System Locality Latency and Bandwidth Information Structure
      • 5.2.27.5. Memory Side Cache Information Structure
    • 5.2.28. Platform Debug Trigger Table (PDTT)
      • 5.2.28.1. PDTT PCC Sub Channel
      • 5.2.28.2. PDTT PCC Trigger Order
      • 5.2.28.3. Example: OS Invoking Multiple Debug Triggers
    • 5.2.29. Processor Properties Topology Table (PPTT)
      • 5.2.29.1. Processor hierarchy node structure (Type 0)
      • 5.2.29.2. Cache Type Structure - Type 1
    • 5.2.30. Platform Health Assessment Table (PHAT)
      • 5.2.30.1. Platform Health Assessment Record Format
      • 5.2.30.2. Platform Health Assessment Record Type Format
      • 5.2.30.3. Firmware Version Data Record Structure
      • 5.2.30.4. Firmware Health Data Record Structure
  • 5.3. ACPI Namespace
    • 5.3.1. Predefined Root Namespaces
    • 5.3.2. Objects
  • 5.4. Definition Block Encoding
    • 5.4.1. AML Encoding
    • 5.4.2. Definition Block Loading
  • 5.5. Control Methods and the ACPI Source Language (ASL)
    • 5.5.1. ASL Statements
    • 5.5.2. Control Method Execution
      • 5.5.2.1. Arguments
      • 5.5.2.2. Method Calling Convention
      • 5.5.2.3. Local Variables and Locally Created Data Objects
      • 5.5.2.4. Access to Operation Regions
  • 5.6. ACPI Event Programming Model
    • 5.6.1. ACPI Event Programming Model Components
    • 5.6.2. Types of ACPI Events
    • 5.6.3. Fixed Event Handling
    • 5.6.4. General-Purpose Event Handling
      • 5.6.4.1. _Exx, _Lxx, and _Qxx Methods for GPE Processing
      • 5.6.4.2. GPE Wake Events
    • 5.6.5. GPIO-signaled ACPI Events
      • 5.6.5.1. Declaring GPIO Controller Devices
      • 5.6.5.2. _AEI Object for GPIO-signaled Events
      • 5.6.5.3. The Event (_EVT) Method for Handling GPIO-signaled Events
    • 5.6.6. Device Object Notifications
    • 5.6.7. Device Class-Specific Objects
    • 5.6.8. Predefined ACPI Names for Objects, Methods, and Resources
    • 5.6.9. Interrupt-signaled ACPI events
      • 5.6.9.1. Declaring Generic Event Device
      • 5.6.9.2. _CRS Object for Interrupt-signaled Events
      • 5.6.9.3. The Event (_EVT) Method for Handling Interrupt-signaled Events
      • 5.6.9.4. GED Wake Events
    • 5.6.10. Managing a Wake Event Using Device _PRW Objects
  • 5.7. Predefined Objects
    • 5.7.1. \_GL (Global Lock Mutex)
    • 5.7.2. \_OSI (Operating System Interfaces)
      • 5.7.2.1. _OSI Examples
    • 5.7.3. \_OS (OS Name Object)
    • 5.7.4. \_REV (Revision Data Object)
    • 5.7.5. \_DLM (DeviceLock Mutex)
  • 5.8. System Configuration Objects
    • 5.8.1. \_PIC Method
• 6. Device Configuration
  • 6.1. Device Identification Objects
    • 6.1.1. _ADR (Address)
    • 6.1.2. _CID (Compatible ID)
    • 6.1.3. _CLS (Class Code)
    • 6.1.4. _DDN (DOS Device Name)
    • 6.1.5. _HID (Hardware ID)
    • 6.1.6. _HRV (Hardware Revision)
    • 6.1.7. _MLS (Multiple Language String)
    • 6.1.8. _PLD (Physical Location of Device)
    • 6.1.9. _SUB (Subsystem ID)
    • 6.1.10. _STR (String)
    • 6.1.11. _SUN (Slot User Number)
    • 6.1.12. _UID (Unique ID)
  • 6.2. Device Configuration Objects
    • 6.2.1. _CDM (Clock Domain)
    • 6.2.2. _CRS (Current Resource Settings)
    • 6.2.3. _DIS (Disable)
    • 6.2.4. _DMA (Direct Memory Access)
    • 6.2.5. _DSD (Device Specific Data)
    • 6.2.6. _FIX (Fixed Register Resource Provider)
    • 6.2.7. _GSB (Global System Interrupt Base)
    • 6.2.8. _HPP (Hot Plug Parameters)
    • 6.2.9. _HPX (Hot Plug Parameter Extensions)
      • 6.2.9.1. PCI Setting Record (Type 0)
      • 6.2.9.2. PCI-X Setting Record (Type 1)
      • 6.2.9.3. PCI Express Setting Record (Type 2)
      • 6.2.9.4. PCI Express Descriptor Setting Record (Type 3)
      • 6.2.9.5. _HPX Example
    • 6.2.10. _MAT (Multiple APIC Table Entry)
    • 6.2.11. _OSC (Operating System Capabilities)
      • 6.2.11.1. Rules for Evaluating _OSC
      • 6.2.11.2. Platform-Wide OSPM Capabilities
      • 6.2.11.3. Operating System Capabilities (_OSC) for USB
    • 6.2.12. _PRS (Possible Resource Settings)
    • 6.2.13. _PRT (PCI Routing Table)
      • 6.2.13.1. Example: Using _PRT to Describe PCI IRQ Routing
    • 6.2.14. _PXM (Proximity)
    • 6.2.15. _SLI (System Locality Information)
    • 6.2.16. _SRS (Set Resource Settings)
    • 6.2.17. _CCA (Cache Coherency Attribute)
      • 6.2.17.1. _CCA Example ASL:
    • 6.2.18. _HMA(Heterogeneous Memory Attributes)
  • 6.3. Device Insertion, Removal, and Status Objects
    • 6.3.1. _EDL (Eject Device List)
    • 6.3.2. _EJD (Ejection Dependent Device)
    • 6.3.3. _EJx (Eject)
    • 6.3.4. _LCK (Lock)
    • 6.3.5. _OST (OSPM Status Indication)
      • 6.3.5.1. Processing Sequence for Graceful Shutdown Request:
      • 6.3.5.2. Processing Sequence for Error Disconnect Recover
    • 6.3.6. _RMV (Remove)
    • 6.3.7. _STA (Device Status)
  • 6.4. Resource Data Types for ACPI
    • 6.4.1. ASL Macros for Resource Descriptors
    • 6.4.2. Small Resource Data Type
      • 6.4.2.1. IRQ Descriptor
      • 6.4.2.2. DMA Descriptor
      • 6.4.2.3. Start Dependent Functions Descriptor
      • 6.4.2.4. End Dependent Functions Descriptor
      • 6.4.2.5. I/O Port Descriptor
      • 6.4.2.6. Fixed Location I/O Port Descriptor
      • 6.4.2.7. Fixed DMA Descriptor
      • 6.4.2.8. Vendor-Defined Descriptor, Type 0
      • 6.4.2.9. End Tag
    • 6.4.3. Large Resource Data Type
      • 6.4.3.1. 24-Bit Memory Range Descriptor
      • 6.4.3.2. Vendor-Defined Descriptor, Type 1
      • 6.4.3.3. 32-Bit Memory Range Descriptor
      • 6.4.3.4. 32-Bit Fixed Memory Range Descriptor
      • 6.4.3.5. Address Space Resource Descriptors
      • 6.4.3.6. Extended Interrupt Descriptor
      • 6.4.3.7. Generic Register Descriptor
      • 6.4.3.8. Connection Descriptors
      • 6.4.3.9. Pin Function Descriptor
      • 6.4.3.10. Pin Configuration Descriptor
      • 6.4.3.11. Pin Group Descriptor
      • 6.4.3.12. Pin Group Function Descriptor
      • 6.4.3.13. Pin Group Configuration Descriptor
  • 6.5. Other Objects and Control Methods
    • 6.5.1. _INI (Init)
    • 6.5.2. _DCK (Dock)
    • 6.5.3. _BDN (BIOS Dock Name)
    • 6.5.4. _REG (Region)
    • 6.5.5. _BBN (Base Bus Number)
    • 6.5.6. _SEG (Segment)
    • 6.5.7. _GLK (Global Lock)
    • 6.5.8. _DEP (Operation Region Dependencies)
    • 6.5.9. _FIT (Firmware Interface Table)
    • 6.5.10. NVDIMM Label Methods
      • 6.5.10.1. _LSI (Label Storage Information)
      • 6.5.10.2. _LSR (Label Storage Read)
      • 6.5.10.3. _LSW (Label Storage Write)
    • 6.5.11. _CBR (CXL Host Bridge Register Info)
• 7. Power and Performance Management
  • 7.1. Power Resource Objects and the Power Management Models
  • 7.2. Declaring a Power Resource Object
    • 7.2.1. Defined Methods for a Power Resource
    • 7.2.2. _OFF
    • 7.2.3. _ON
    • 7.2.4. _STA (Power Resource Status)
    • 7.2.5. Passive Power Resources
  • 7.3. Device Power Management Objects
    • 7.3.1. _DSW (Device Sleep Wake)
    • 7.3.2. _PS0 (Power State 0)
    • 7.3.3. _PS1 (Power State 1)
    • 7.3.4. _PS2 (Power State 2)
    • 7.3.5. _PS3 (Power State 3)
    • 7.3.6. _PSC (Power State Current)
    • 7.3.7. _PSE (Power State for Enumeration)
    • 7.3.8. _PR0 (Power Resources for D0)
    • 7.3.9. _PR1 (Power Resources for D1)
    • 7.3.10. _PR2 (Power Resources for D2)
    • 7.3.11. _PR3 (Power Resources for D3hot)
    • 7.3.12. _PRE (Power Resources for Enumeration)
    • 7.3.13. _PRW (Power Resources for Wake)
    • 7.3.14. _PSW (Power State Wake)
    • 7.3.15. _IRC (In Rush Current)
    • 7.3.16. _S1D (S1 Device State)
    • 7.3.17. _S2D (S2 Device State)
    • 7.3.18. _S3D (S3 Device State)
    • 7.3.19. _S4D (S4 Device State)
    • 7.3.20. _S0W (S0 Device Wake State)
    • 7.3.21. _S1W (S1 Device Wake State)
    • 7.3.22. _S2W (S2 Device Wake State)
    • 7.3.23. _S3W (S3 Device Wake State)
    • 7.3.24. _S4W (S4 Device Wake State)
    • 7.3.25. _RST (Device Reset)
    • 7.3.26. _PRR (Power Resource for Reset)
  • 7.4. OEM-Supplied System-Level Control Methods
    • 7.4.1. \_PTS (Prepare To Sleep)
    • 7.4.2. \_Sx (System States)
      • 7.4.2.1. System \_S0 State (Working)
      • 7.4.2.2. System \_S1 State (Sleeping with Processor Context Maintained)
      • 7.4.2.3. System \_S2 State
      • 7.4.2.4. System \_S3 State
      • 7.4.2.5. System \_S4 State
      • 7.4.2.6. System \_S5 State (Soft Off)
    • 7.4.3. \_SWS (System Wake Source)
    • 7.4.4. \_TTS (Transition To State)
    • 7.4.5. \_WAK (System Wake)
  • 7.5. OSPM usage of _PTS, _TTS, and _WAK
• 8. Processor Configuration and Control
  • 8.1. Processor Power States
    • 8.1.1. Processor Power State C0
    • 8.1.2. Processor Power State C1
    • 8.1.3. Processor Power State C2
    • 8.1.4. Processor Power State C3
    • 8.1.5. Additional Processor Power States
  • 8.2. Flushing Caches
  • 8.3. Power, Performance, and Throttling State Dependencies
  • 8.4. Declaring Processors
    • 8.4.1. Processor Power State Control
      • 8.4.1.1. _CST (C States)
      • 8.4.1.2. _CSD (C-State Dependency)
    • 8.4.2. Processor Hierarchy
      • 8.4.2.1. Processor Container Device
    • 8.4.3. Lower Power Idle States
      • 8.4.3.1. Hierarchical Idle States
      • 8.4.3.2. Idle State Coordination
      • 8.4.3.3. _LPI (Low Power Idle States)
      • 8.4.3.4. _RDI (Resource Dependencies for Idle)
      • 8.4.3.5. Compatibility
    • 8.4.4. Processor Throttling Controls
      • 8.4.4.1. _PTC (Processor Throttling Control)
      • 8.4.4.2. _TSS (Throttling Supported States)
      • 8.4.4.3. _TPC (Throttling Present Capabilities)
      • 8.4.4.4. _TSD (T-State Dependency)
      • 8.4.4.5. _TDL (T-state Depth Limit)
    • 8.4.5. Processor Performance Control
      • 8.4.5.1. _PCT (Performance Control)
      • 8.4.5.2. _PSS (Performance Supported States)
      • 8.4.5.3. _PPC (Performance Present Capabilities)
      • 8.4.5.4. Processor Performance Control Example
      • 8.4.5.5. _PSD (P-State Dependency)
      • 8.4.5.6. _PDL (P-state Depth Limit)
    • 8.4.6. Collaborative Processor Performance Control
      • 8.4.6.1. _CPC (Continuous Performance Control)
    • 8.4.7. _PPE (Polling for Platform Errors)
  • 8.5. Processor Aggregator Device
    • 8.5.1. Logical Processor Idling
      • 8.5.1.1. _PUR (Processor Utilization Request)
    • 8.5.2. OSPM _OST Evaluation
• 9. ACPI-Defined Devices and Device-Specific Objects
  • 9.1. Device Object Name Collision
    • 9.1.1. _DSM (Device Specific Method)
  • 9.2. \_SI System Indicators
    • 9.2.1. _SST (System Status)
    • 9.2.2. _MSG (Message)
    • 9.2.3. _BLT (Battery Level Threshold)
  • 9.3. Ambient Light Sensor Device
    • 9.3.1. Overview
    • 9.3.2. _ALI (Ambient Light Illuminance)
    • 9.3.3. _ALT (Ambient Light Temperature)
    • 9.3.4. _ALC (Ambient Light Color Chromaticity)
    • 9.3.5. _ALR (Ambient Light Response)
    • 9.3.6. _ALP (Ambient Light Polling)
    • 9.3.7. Ambient Light Sensor Events
    • 9.3.8. Relationship to Backlight Control Methods
  • 9.4. Control Method Lid Device
    • 9.4.1. _LID
  • 9.5. Control Method Power and Sleep Button Devices
  • 9.6. Generic Container Device
  • 9.7. ATA Controller Devices
    • 9.7.1. Objects for Both ATA and SATA Controllers
      • 9.7.1.1. _GTF (Get Task File)
    • 9.7.2. IDE Controller Device
      • 9.7.2.1. IDE Controller-specific Objects
    • 9.7.3. Serial ATA (SATA) Controller Device
      • 9.7.3.1. Definitions
      • 9.7.3.2. Overview
      • 9.7.3.3. SATA controller-specific control methods
  • 9.8. Floppy Controller Device Objects
    • 9.8.1. _FDE (Floppy Disk Enumerate)
    • 9.8.2. _FDI (Floppy Disk Information)
    • 9.8.3. _FDM (Floppy Disk Drive Mode)
  • 9.9. GPE Block Device
    • 9.9.1. Matching Control Methods for Events in a GPE Block Device
  • 9.10. Module Device
  • 9.11. Memory Devices
    • 9.11.1. Address Decoding
    • 9.11.2. Memory Bandwidth Monitoring and Reporting
      • 9.11.2.1. _MBM (Memory Bandwidth Monitoring Data)
      • 9.11.2.2. _MSM (Memory Set Monitoring)
    • 9.11.3. _OSC Definition for Memory Device
    • 9.11.4. Example: Memory Device
  • 9.12. _UPC (USB Port Capabilities)
    • 9.12.1. USB 2.0 Host Controllers and _UPC and _PLD
  • 9.13. PC/AT RTC/CMOS Devices
    • 9.13.1. PC/AT-compatible RTC/CMOS Devices (PNP0B00)
    • 9.13.2. Intel PIIX4-compatible RTC/CMOS Devices (PNP0B01)
    • 9.13.3. Dallas Semiconductor-compatible RTC/CMOS Devices (PNP0B02)
  • 9.14. User Presence Detection Device
    • 9.14.1. _UPD (User Presence Detect)
    • 9.14.2. _UPP (User Presence Polling)
    • 9.14.3. User Presence Sensor Events
  • 9.15. I/O APIC Device
  • 9.16. Time and Alarm Device
    • 9.16.1. Overview
    • 9.16.2. _GCP (Get Capability)
    • 9.16.3. _GRT (Get Real Time)
    • 9.16.4. _SRT (Set Real Time)
    • 9.16.5. _GWS (Get Wake alarm status)
    • 9.16.6. _CWS (Clear Wake alarm status)
    • 9.16.7. _STP (Set Expired Timer Wake Policy)
    • 9.16.8. _STV (Set Timer Value)
    • 9.16.9. _TIP (Expired Timer Wake Policy)
    • 9.16.10. _TIV (Timer Values)
    • 9.16.11. ACPI Wakeup Alarm Events
    • 9.16.12. Relationship to Real Time Clock Alarm
    • 9.16.13. Time and Alarm device as a replacement to the RTC
    • 9.16.14. Relationship to UEFI time source
    • 9.16.15. Example ASL code
  • 9.17. Generic Buttons Device
    • 9.17.1. Button Interrupts
    • 9.17.2. Button Usages and Collections
    • 9.17.3. Generic Buttons Device Example
  • 9.18. NVDIMM Devices
    • 9.18.1. Overview
    • 9.18.2. NVDIMM Root Device
    • 9.18.3. NVDIMM Device
    • 9.18.4. Example
    • 9.18.5. Loading NVDIMM drivers
    • 9.18.6. Hot Plug Support
    • 9.18.7. NVDIMM Root Device _DSMs
      • 9.18.7.1. Input Parameters:
      • 9.18.7.2. Address Range Scrubbing (ARS) Overview
      • 9.18.7.3. Address Range Scrub (ARS) Error Injection Overview
      • 9.18.7.4. Function Index 1 - Query ARS Capabilities
      • 9.18.7.5. Function Index 2 - Start ARS
      • 9.18.7.6. Function Index 3 - Query ARS Status
      • 9.18.7.7. Function Index 4 - Clear Uncorrectable Error
      • 9.18.7.8. Function Index 5 - Translate SPA
      • 9.18.7.9. Function Index 7 - ARS Error Inject
      • 9.18.7.10. Function Index 8 - ARS Error Inject Clear
      • 9.18.7.11. Function Index 9 - ARS Error Inject Status Query
      • 9.18.7.12. Function Index 0xA - Query ARS Error Inject Capabilities
    • 9.18.8. NVDIMM Device Methods
      • 9.18.8.1. _NCH (Get NVDIMM Current Health Information)
      • 9.18.8.2. _NBS (Get NVDIMM Boot Status)
      • 9.18.8.3. _NIC (Get NVDIMM Health Error Injection Capabilities)
      • 9.18.8.4. _NIH (NVDIMM Inject/Clear Health Errors)
      • 9.18.8.5. _NIG (Get NVDIMM Inject Health Error Status)
• 10. Power Source and Power Meter Devices
  • 10.1. Smart Battery Subsystems
    • 10.1.1. ACPI Smart Battery Status Change Notification Requirements
      • 10.1.1.1. Smart Battery Charger
      • 10.1.1.2. Smart Battery Charger with optional System Manager or Selector
      • 10.1.1.3. Smart Battery System Manager
      • 10.1.1.4. Smart Battery Selector
    • 10.1.2. Smart Battery Objects
    • 10.1.3. _SBS (Smart Battery Subsystem)
      • 10.1.3.1. Example: Single Smart Battery Subsystem
      • 10.1.3.2. Multiple Smart Battery Subsystem: Example
  • 10.2. Control Method Batteries
    • 10.2.1. Battery Events
    • 10.2.2. Battery Control Methods
      • 10.2.2.1. _BCT (Battery Charge Time)
      • 10.2.2.2. _BIF (Battery Information)
      • 10.2.2.3. _BIX (Battery Information Extended)
      • 10.2.2.4. _BMA (Battery Measurement Averaging Interval)
      • 10.2.2.5. _BMC (Battery Maintenance Control)
      • 10.2.2.6. _BMD (Battery Maintenance Data)
      • 10.2.2.7. _BMS (Battery Measurement Sampling Time)
      • 10.2.2.8. _BPC (Battery Power Characteristics)
      • 10.2.2.9. _BPS (Battery Power State)
      • 10.2.2.10. _BPT (Battery Power Threshold)
      • 10.2.2.11. _BST (Battery Status)
      • 10.2.2.12. _BTH (Battery Throttle Limit)
      • 10.2.2.13. _BTM (Battery Time)
      • 10.2.2.14. _BTP (Battery Trip Point)
      • 10.2.2.15. _OSC Definition for Control Method Battery
  • 10.3. AC Adapters and Power Source Objects
    • 10.3.1. _PSR (Power Source)
    • 10.3.2. _PCL (Power Consumer List)
    • 10.3.3. _PIF (Power Source Information)
    • 10.3.4. _PRL (Power Source Redundancy List)
  • 10.4. Power Meters
    • 10.4.1. _PMC (Power Meter Capabilities)
    • 10.4.2. _PTP (Power Trip Points)
    • 10.4.3. _PMM (Power Meter Measurement)
    • 10.4.4. _PAI (Power Averaging Interval)
    • 10.4.5. _GAI (Get Averaging Interval)
    • 10.4.6. _SHL (Set Hardware Limit)
    • 10.4.7. _GHL (Get Hardware Limit)
    • 10.4.8. _PMD (Power Metered Devices)
  • 10.5. Wireless Power Controllers
    • 10.5.1. Wireless Power Calibration Device
    • 10.5.2. Wireless Power Calibration (_WPC)
    • 10.5.3. Wireless Power Polling (_WPP)
  • 10.6. Wireless Power Calibration Event
  • 10.7. Example: Power Source and Power Meter Namespace
• 11. Thermal Management
  • 11.1. Thermal Control
    • 11.1.1. Active, Passive, and Critical Policies
    • 11.1.2. Dynamically Changing Cooling Temperature Trip Points
      • 11.1.2.1. OSPM Change of Cooling Policy
      • 11.1.2.2. Resetting Cooling Temperatures to Adjust to Bay Device Insertion or Removal
      • 11.1.2.3. Resetting Cooling Temperatures to Implement Hysteresis
    • 11.1.3. Detecting Temperature Changes
      • 11.1.3.1. Temperature Change Notifications
      • 11.1.3.2. Polling
    • 11.1.4. Active Cooling
    • 11.1.5. Passive Cooling
      • 11.1.5.1. Processor Clock Throttling
    • 11.1.6. Critical Shutdown
  • 11.2. Cooling Preferences
    • 11.2.1. Evaluating Thermal Device Lists
    • 11.2.2. Evaluating Device Thermal Relationship Information
    • 11.2.3. Fan Device Notifications
  • 11.3. Fan Device
    • 11.3.1. Fan Objects
      • 11.3.1.1. _FIF (Fan Information)
      • 11.3.1.2. _FPS (Fan Performance States)
      • 11.3.1.3. _FSL (Fan Set Level)
      • 11.3.1.4. _FST (Fan Status)
  • 11.4. Thermal Objects
    • 11.4.1. _ACx (Active Cooling)
    • 11.4.2. _ALx (Active List)
    • 11.4.3. _ART (Active Cooling Relationship Table)
    • 11.4.4. _CRT (Critical Temperature)
    • 11.4.5. _CR3 (Warm/Standby Temperature)
    • 11.4.6. _DTI (Device Temperature Indication)
    • 11.4.7. _HOT (Hot Temperature)
    • 11.4.8. _MTL (Minimum Throttle Limit)
    • 11.4.9. _NTT (Notification Temperature Threshold)
    • 11.4.10. _PSL (Passive List)
    • 11.4.11. _PSV (Passive)
    • 11.4.12. _RTV (Relative Temperature Values)
    • 11.4.13. _SCP (Set Cooling Policy)
    • 11.4.14. _STR (String)
    • 11.4.15. _TC1 (Thermal Constant 1)
    • 11.4.16. _TC2 (Thermal Constant 2)
    • 11.4.17. _TFP (Thermal fast Sampling Period)
    • 11.4.18. _TMP (Temperature)
    • 11.4.19. _TPT (Trip Point Temperature)
    • 11.4.20. _TRT (Thermal Relationship Table)
    • 11.4.21. _TSN (Thermal Sensor Device)
    • 11.4.22. _TSP (Thermal Sampling Period)
    • 11.4.23. _TST (Temperature Sensor Threshold)
    • 11.4.24. _TZD (Thermal Zone Devices)
    • 11.4.25. _TZM (Thermal Zone Member)
    • 11.4.26. _TZP (Thermal Zone Polling)
  • 11.5. Native OS Device Driver Thermal Interfaces
  • 11.6. Thermal Zone Interface Requirements
  • 11.7. Thermal Zone Examples
    • 11.7.1. Example: The Basic Thermal Zone
    • 11.7.2. Example: Multiple-Speed Fans
    • 11.7.3. Example: Thermal Zone with Multiple Devices
• 12. ACPI Embedded Controller Interface Specification
  • 12.1. Embedded Controller Interface Description
  • 12.2. Embedded Controller Register Descriptions
    • 12.2.1. Embedded Controller Status, EC_SC (R)
    • 12.2.2. Embedded Controller Command, EC_SC (W)
    • 12.2.3. Embedded Controller Data, EC_DATA (R/W)
  • 12.3. Embedded Controller Command Set
    • 12.3.1. Read Embedded Controller, RD_EC (0x80)
    • 12.3.2. Write Embedded Controller, WR_EC (0x81)
    • 12.3.3. Burst Enable Embedded Controller, BE_EC (0x82)
    • 12.3.4. Burst Disable Embedded Controller, BD_EC (0x83)
    • 12.3.5. Query Embedded Controller, QR_EC (0x84)
  • 12.4. SMBus Host Controller Notification Header (Optional), OS_SMB_EVT
  • 12.5. Embedded Controller Firmware
  • 12.6. Interrupt Model
    • 12.6.1. Event Interrupt Model
    • 12.6.2. Command Interrupt Model
  • 12.7. Embedded Controller Interfacing Algorithms
  • 12.8. Embedded Controller Description Information
  • 12.9. SMBus Host Controller Interface via Embedded Controller
    • 12.9.1. Register Description
      • 12.9.1.1. Status Register, SMB_STS
      • 12.9.1.2. Protocol Register, SMB_PRTCL
      • 12.9.1.3. Address Register, SMB_ADDR
      • 12.9.1.4. Command Register, SMB_CMD
      • 12.9.1.5. Data Register Array, SMB_DATA[i], i=0-31
      • 12.9.1.6. Block Count Register, SMB_BCNT
      • 12.9.1.7. Alarm Address Register, SMB_ALRM_ADDR
      • 12.9.1.8. Alarm Data Registers, SMB_ALRM_DATA[0], SMB_ALRM_DATA[1]
    • 12.9.2. Protocol Description
      • 12.9.2.1. Write Quick
      • 12.9.2.2. Read Quick
      • 12.9.2.3. Send Byte
      • 12.9.2.4. Receive Byte
      • 12.9.2.5. Write Byte
      • 12.9.2.6. Read Byte
      • 12.9.2.7. Write Word
      • 12.9.2.8. Read Word
      • 12.9.2.9. Write Block
      • 12.9.2.10. Read Block
      • 12.9.2.11. Process Call
      • 12.9.2.12. Block Write-Block Read Process Call
      • 12.9.2.13. SMBus Register Set
  • 12.10. SMBus Devices
    • 12.10.1. SMBus Device Access Restrictions
    • 12.10.2. SMBus Device Command Access Restriction
  • 12.11. Defining an Embedded Controller Device in ACPI Namespace
    • 12.11.1. Example: EC Definition ASL Code
  • 12.12. Defining an EC SMBus Host Controller in ACPI Namespace
    • 12.12.1. Example: EC SMBus Host Controller ASL-Code
• 13. ACPI System Management Bus Interface Specification
  • 13.1. SMBus Overview
    • 13.1.1. SMBus Slave Addresses
    • 13.1.2. SMBus Protocols
    • 13.1.3. SMBus Status Codes
    • 13.1.4. SMBus Command Values
  • 13.2. Accessing the SMBus from ASL Code
    • 13.2.1. Declaring SMBus Host Controller Objects
    • 13.2.2. Declaring SMBus Devices
    • 13.2.3. Declaring SMBus Operation Regions
    • 13.2.4. Declaring SMBus Fields
    • 13.2.5. Declaring and Using an SMBus Data Buffer
  • 13.3. Using the SMBus Protocols
    • 13.3.1. Read/Write Quick (SMBQuick)
    • 13.3.2. Send/Receive Byte (SMBSendReceive)
    • 13.3.3. Read/Write Byte (SMBByte)
    • 13.3.4. Read/Write Word (SMBWord)
    • 13.3.5. Read/Write Block (SMBBlock)
    • 13.3.6. Word Process Call (SMBProcessCall)
    • 13.3.7. Block Process Call (SMBBlockProcessCall)
• 14. Platform Communications Channel (PCC)
  • 14.1. Platform Communications Channel Table
    • 14.1.1. Platform Communications Channel Global Flags
    • 14.1.2. Platform Communications Channel Subspace Structures
    • 14.1.3. Generic Communications Subspace Structure (type 0)
    • 14.1.4. HW-Reduced Communications Subspace Structure (type 1)
    • 14.1.5. HW-Reduced Communications Subspace Structure (type 2)
    • 14.1.6. Extended PCC subspaces (types 3 and 4)
    • 14.1.7. HW Registers based Communications Subspace Structure (Type 5)
  • 14.2. Generic Communications Channel Shared Memory Region
    • 14.2.1. Generic Communications Channel Command Field
    • 14.2.2. Generic Communications Channel Status Field
  • 14.3. Extended PCC Subspace Shared Memory Region
  • 14.4. Reduced PCC Subspace Shared Memory Region
  • 14.5. Doorbell Protocol
  • 14.6. Platform Notification
    • 14.6.1. Platform Notification for Subspace Types 0, 1 and 2
    • 14.6.2. Platform Notification for Responder PCC subspaces (type 4)
  • 14.7. Referencing the PCC address space
• 15. System Address Map Interfaces
  • 15.1. INT 15H, E820H - Query System Address Map
  • 15.2. E820 Assumptions and Limitations
  • 15.3. UEFI GetMemoryMap() Boot Services Function
  • 15.4. UEFI Assumptions and Limitations
  • 15.5. Example Address Map
  • 15.6. Example: Operating System Usage
• 16. Waking and Sleeping
  • 16.1. Sleeping States
    • 16.1.1. S1 Sleeping State
      • 16.1.1.1. Example 1: S1 Sleeping State Implementation
      • 16.1.1.2. Example 2: S1 Sleeping State Implementation
    • 16.1.2. S2 Sleeping State
      • 16.1.2.1. Example: S2 Sleeping State Implementation
    • 16.1.3. S3 Sleeping State
      • 16.1.3.1. Example: S3 Sleeping State Implementation
    • 16.1.4. S4 Sleeping State
      • 16.1.4.1. Operating System-Initiated S4 Transition
      • 16.1.4.2. The S4BIOS Transition
    • 16.1.5. S5 Soft Off State
    • 16.1.6. Transitioning from the Working to the Sleeping State
    • 16.1.7. Transitioning from the Working to the Soft Off State
  • 16.2. Flushing Caches
  • 16.3. Initialization
    • 16.3.1. Placing the System in ACPI Mode
    • 16.3.2. Platform Boot Firmware Initialization of Memory
    • 16.3.3. OS Loading
    • 16.3.4. Exiting ACPI Mode
• 17. Non-Uniform Memory Access (NUMA) Architecture Platforms
  • 17.1. NUMA Node
  • 17.2. System Locality
    • 17.2.1. System Resource Affinity Table Definition
    • 17.2.2. System Resource Affinity Update
  • 17.3. System Locality Distance Information
    • 17.3.1. Online Hot Plug
    • 17.3.2. Impact to Existing Localities
  • 17.4. Heterogeneous Memory Attributes Information
    • 17.4.1. Online Hot Plug
    • 17.4.2. Impact to Existing Localities
• 18. ACPI Platform Error Interfaces (APEI)
  • 18.1. Hardware Errors and Error Sources
  • 18.2. Relationship between OSPM and System Firmware
  • 18.3. Error Source Discovery
    • 18.3.1. Boot Error Source
    • 18.3.2. ACPI Error Source
      • 18.3.2.1. IA-32 Architecture Machine Check Exception
      • 18.3.2.2. IA-32 Architecture Corrected Machine Check
      • 18.3.2.3. IA-32 Architecture Non-Maskable Interrupt
      • 18.3.2.4. PCI Express Root Port AER Structure
      • 18.3.2.5. PCI Express Device AER Structure
      • 18.3.2.6. PCI Express/PCI-X Bridge AER Structure
      • 18.3.2.7. Generic Hardware Error Source
      • 18.3.2.8. Generic Hardware Error Source version 2 (GHESv2 - Type 10)
      • 18.3.2.9. Hardware Error Notification
      • 18.3.2.10. IA-32 Architecture Deferred Machine Check
  • 18.4. Firmware First Error Handling
    • 18.4.1. Example: Firmware First Handling Using NMI Notification
  • 18.5. Error Serialization
    • 18.5.1. Serialization Action Table
      • 18.5.1.1. Serialization Actions
      • 18.5.1.2. Serialization Instruction Entries
      • 18.5.1.3. Error Record Serialization Information
    • 18.5.2. Operations
      • 18.5.2.1. Writing
      • 18.5.2.2. Reading
      • 18.5.2.3. Clearing
      • 18.5.2.4. Usage
  • 18.6. Error Injection
    • 18.6.1. Error Injection Table (EINJ)
    • 18.6.2. Injection Instruction Entries
    • 18.6.3. Injection Instructions
    • 18.6.4. Error Types
    • 18.6.5. Trigger Action Table
    • 18.6.6. Error Injection Operation
  • 18.7. GHES_ASSIST Error Reporting
    • 18.7.1. GHES_ASSIST on Machine Check Architecture
• 19. ACPI Source Language (ASL) Reference
  • 19.1. ASL 2.0 Symbolic Operators and Expressions
  • 19.2. ASL Language Grammar
    • 19.2.1. ASL Grammar Notation
    • 19.2.2. ASL Name and Pathname Terms
    • 19.2.3. ASL Root and Secondary Terms
    • 19.2.4. ASL Data and Constant Terms
    • 19.2.5. ASL Opcode Terms
    • 19.2.6. ASL Primary (Terminal) Terms
    • 19.2.7. ASL Parameter Keyword Terms
    • 19.2.8. ASL Resource Template Terms
  • 19.3. ASL Concepts
    • 19.3.1. ASL Names
      • 19.3.1.1. _T_x Reserved Object Names
    • 19.3.2. ASL Literal Constants
      • 19.3.2.1. Integers
      • 19.3.2.2. Strings
    • 19.3.3. ASL Resource Templates
    • 19.3.4. ASL Macros
    • 19.3.5. ASL Data Types
      • 19.3.5.1. Data Type Conversion Overview
      • 19.3.5.2. Explicit Data Type Conversions
      • 19.3.5.3. Implicit Data Type Conversions
      • 19.3.5.4. Implicit Source Operand Conversion
      • 19.3.5.5. Implicit Result Object Conversion
      • 19.3.5.6. Data Types and Type Conversions
      • 19.3.5.7. Data Type Conversion Rules
      • 19.3.5.8. Rules for Storing and Copying Objects
  • 19.4. ASL Operators Summary
  • 19.5. ASL Operator Summary by Type
  • 19.6. ASL Operator Reference
    • 19.6.1. AccessAs (Change Field Unit Access)
    • 19.6.2. Acquire (Acquire a Mutex)
    • 19.6.3. Add (Integer Add)
    • 19.6.4. Alias (Declare Name Alias)
    • 19.6.5. And (Integer Bitwise And)
    • 19.6.6. Argx (Method Argument Data Objects)
    • 19.6.7. BankField (Declare Bank/Data Field)
    • 19.6.8. Break (Break from While)
    • 19.6.9. BreakPoint (Execution Break Point)
    • 19.6.10. Buffer (Declare Buffer Object)
    • 19.6.11. Case (Expression for Conditional Execution)
    • 19.6.12. Concatenate (Concatenate Data)
    • 19.6.13. ConcatenateResTemplate (Concatenate Resource Templates)
    • 19.6.14. CondRefOf (Create Object Reference Conditionally)
    • 19.6.15. Connection (Declare Field Connection Attributes)
    • 19.6.16. Continue (Continue Innermost Enclosing While)
    • 19.6.17. CopyObject (Copy and Store Object)
    • 19.6.18. CreateBitField (Create 1-Bit Buffer Field)
    • 19.6.19. CreateByteField (Create 8-Bit Buffer Field)
    • 19.6.20. CreateDWordField (Create 32-Bit Buffer Field)
    • 19.6.21. CreateField (Create Arbitrary Length Buffer Field)
    • 19.6.22. CreateQWordField (Create 64-Bit Buffer Field)
    • 19.6.23. CreateWordField (Create 16-Bit Buffer Field)
    • 19.6.24. CSI2Bus (CSI-2 Serial Bus Connection Resource Descriptor Macro)
    • 19.6.25. DataTableRegion (Create Data Table Operation Region)
    • 19.6.26. Debug (Debugger Output)
    • 19.6.27. Decrement (Integer Decrement)
    • 19.6.28. Default (Default Execution Path in Switch)
    • 19.6.29. DefinitionBlock (Declare Definition Block)
    • 19.6.30. DerefOf (Dereference an Object Reference)
    • 19.6.31. Device (Declare Device Package)
    • 19.6.32. Divide (Integer Divide)
    • 19.6.33. DMA (DMA Resource Descriptor Macro)
    • 19.6.34. DWordIO (DWord IO Resource Descriptor Macro)
    • 19.6.35. DWordMemory (DWord Memory Resource Descriptor Macro)
    • 19.6.36. DWordSpace (DWord Space Resource Descriptor Macro)
    • 19.6.37. EISAID (EISA ID String To Integer Conversion Macro)
    • 19.6.38. Else (Alternate Execution)
    • 19.6.39. ElseIf (Alternate/Conditional Execution)
    • 19.6.40. EndDependentFn (End Dependent Function Resource Descriptor Macro)
    • 19.6.41. Event (Declare Event Synchronization Object)
    • 19.6.42. ExtendedIO (Extended IO Resource Descriptor Macro)
    • 19.6.43. ExtendedMemory (Extended Memory Resource Descriptor Macro)
    • 19.6.44. ExtendedSpace (Extended Address Space Resource Descriptor Macro)
    • 19.6.45. External (Declare External Objects)
    • 19.6.46. Fatal (Fatal Error Check)
    • 19.6.47. Field (Declare Field Objects)
    • 19.6.48. FindSetLeftBit (Find First Set Left Bit)
    • 19.6.49. FindSetRightBit (Find First Set Right Bit)
    • 19.6.50. FixedDMA (DMA Resource Descriptor Macro)
    • 19.6.51. FixedIO (Fixed IO Resource Descriptor Macro)
    • 19.6.52. For (Conditional Loop)
    • 19.6.53. Fprintf (Create and Store formatted string)
    • 19.6.54. FromBCD (Convert BCD To Integer)
    • 19.6.55. Function (Declare Control Method)
    • 19.6.56. GpioInt (GPIO Interrupt Connection Resource Descriptor Macro)
    • 19.6.57. GpioIo (GPIO Connection IO Resource Descriptor Macro)
    • 19.6.58. I2CSerialBusV2 (I2C Serial Bus Connection Resource Descriptor (Version 2) Macro)
    • 19.6.59. If (Conditional Execution)
    • 19.6.60. Include (Include Additional ASL File)
    • 19.6.61. Increment (Integer Increment)
    • 19.6.62. Index (Indexed Reference To Member Object)
      • 19.6.62.1. Index with Packages
      • 19.6.62.2. Index with Buffers
      • 19.6.62.3. Index with Strings
    • 19.6.63. IndexField (Declare Index/Data Fields)
    • 19.6.64. Interrupt (Interrupt Resource Descriptor Macro)
    • 19.6.65. IO (IO Resource Descriptor Macro)
    • 19.6.66. IRQ (Interrupt Resource Descriptor Macro)
    • 19.6.67. IRQNoFlags (Interrupt Resource Descriptor Macro)
    • 19.6.68. LAnd (Logical And)
    • 19.6.69. LEqual (Logical Equal)
    • 19.6.70. LGreater (Logical Greater)
    • 19.6.71. LGreaterEqual (Logical Greater Than Or Equal)
    • 19.6.72. LLess (Logical Less)
    • 19.6.73. LLessEqual (Logical Less Than Or Equal)
    • 19.6.74. LNot (Logical Not)
    • 19.6.75. LNotEqual (Logical Not Equal)
    • 19.6.76. Load (Load Definition Block)
    • 19.6.77. LoadTable (Load Definition Block From XSDT)
    • 19.6.78. Localx (Method Local Data Objects)
    • 19.6.79. LOr (Logical Or)
    • 19.6.80. Match (Find Object Match)
    • 19.6.81. Memory24 (Memory Resource Descriptor Macro)
    • 19.6.82. Memory32 (Memory Resource Descriptor Macro)
    • 19.6.83. Memory32Fixed (Memory Resource Descriptor Macro)
    • 19.6.84. Method (Declare Control Method)
    • 19.6.85. Mid (Extract Portion of Buffer or String)
    • 19.6.86. Mod (Integer Modulo)
    • 19.6.87. Multiply (Integer Multiply)
    • 19.6.88. Mutex (Declare Synchronization/Mutex Object)
    • 19.6.89. Name (Declare Named Object)
    • 19.6.90. NAnd (Integer Bitwise Nand)
    • 19.6.91. NoOp Code (No Operation)
    • 19.6.92. NOr (Integer Bitwise Nor)
    • 19.6.93. Not (Integer Bitwise Not)
    • 19.6.94. Notify (Notify Object of Event)
    • 19.6.95. Offset (Change Current Field Unit Offset)
    • 19.6.96. ObjectType (Get Object Type)
    • 19.6.97. One (Constant One Integer)
    • 19.6.98. Ones (Constant Ones Integer)
    • 19.6.99. OperationRegion (Declare Operation Region)
    • 19.6.100. Or (Integer Bitwise Or)
    • 19.6.101. Package (Declare Package Object)
    • 19.6.102. PinConfig (Pin Configuration Descriptor Macro)
    • 19.6.103. PinFunction (Pin Function Descriptor Macro)
    • 19.6.104. PinGroup (Pin Group Descriptor Macro)
    • 19.6.105. PinGroupConfig (Pin Group Configuration Descriptor Macro)
    • 19.6.106. PinGroupFunction (Pin Group Function Configuration Descriptor Macro)
    • 19.6.107. PowerResource (Declare Power Resource)
    • 19.6.108. Printf (Create and Store formatted string)
    • 19.6.109. QWordIO (QWord IO Resource Descriptor Macro)
    • 19.6.110. QWordMemory (QWord Memory Resource Descriptor Macro)
    • 19.6.111. QWordSpace (QWord Space Resource Descriptor Macro)
    • 19.6.112. RawDataBuffer (Raw Data Buffer)
    • 19.6.113. RefOf (Create Object Reference)
    • 19.6.114. Register (Generic Register Resource Descriptor Macro)
    • 19.6.115. Release (Release a Mutex Synchronization Object)
    • 19.6.116. Reset (Reset an Event Synchronization Object)
    • 19.6.117. ResourceTemplate (Resource To Buffer Conversion Macro)
    • 19.6.118. Return (Return from Method Execution)
    • 19.6.119. Revision (Constant Revision Integer)
    • 19.6.120. Scope (Open Named Scope)
    • 19.6.121. ShiftLeft (Integer Shift Left)
    • 19.6.122. ShiftRight (Integer Shift Right)
    • 19.6.123. Signal (Signal a Synchronization Event)
    • 19.6.124. SizeOf (Get Data Object Size)
    • 19.6.125. Sleep (Milliseconds Sleep)
    • 19.6.126. SPISerialBusV2 (SPI Serial Bus Connection Resource Descriptor (Version 2) Macro)
    • 19.6.127. Stall (Stall for a Short Time)
    • 19.6.128. StartDependentFn (Start Dependent Function Resource Descriptor Macro)
    • 19.6.129. StartDependentFnNoPri (Start Dependent Function Resource Descriptor Macro)
    • 19.6.130. Store (Store an Object)
    • 19.6.131. Subtract (Integer Subtract)
    • 19.6.132. Switch (Select Code To Execute Based On Expression)
    • 19.6.133. ThermalZone (Declare Thermal Zone)
    • 19.6.134. Timer (Get 64-Bit Timer Value)
    • 19.6.135. ToBCD (Convert Integer to BCD)
    • 19.6.136. ToBuffer (Convert Data to Buffer)
    • 19.6.137. ToDecimalString (Convert Data to Decimal String)
    • 19.6.138. ToHexString (Convert Data to Hexadecimal String)
    • 19.6.139. ToInteger (Convert Data to Integer)
    • 19.6.140. ToPLD (Creates a _PLD Buffer Object)
    • 19.6.141. ToString (Convert Buffer To String)
    • 19.6.142. ToUUID (Convert String to UUID Macro)
    • 19.6.143. UARTSerialBusV2 (UART Serial Bus Connection Resource Descriptor Version 2 Macro)
    • 19.6.144. Unicode (String To Unicode Conversion Macro)
    • 19.6.145. VendorLong (Long Vendor Resource Descriptor)
    • 19.6.146. VendorShort (Short Vendor Resource Descriptor)
    • 19.6.147. Wait (Wait for a Synchronization Event)
    • 19.6.148. While (Conditional Loop)
    • 19.6.149. WordBusNumber (Word Bus Number Resource Descriptor Macro)
    • 19.6.150. WordIO (Word IO Resource Descriptor Macro)
    • 19.6.151. WordSpace (Word Space Resource Descriptor Macro)
    • 19.6.152. XOr (Integer Bitwise Xor)
    • 19.6.153. Zero (Constant Zero Integer)
• 20. ACPI Machine Language (AML) Specification
  • 20.1. Notation Conventions
  • 20.2. AML Grammar Definition
    • 20.2.1. Table and Table Header Encoding
    • 20.2.2. Name Objects Encoding
    • 20.2.3. Data Objects Encoding
    • 20.2.4. Package Length Encoding
    • 20.2.5. Term Objects Encoding
      • 20.2.5.1. Namespace Modifier Objects Encoding
      • 20.2.5.2. Named Objects Encoding
      • 20.2.5.3. Statement Opcodes Encoding
      • 20.2.5.4. Expression Opcodes Encoding
    • 20.2.6. Miscellaneous Objects Encoding
      • 20.2.6.1. Arg Objects Encoding
      • 20.2.6.2. Local Objects Encoding
      • 20.2.6.3. Debug Objects Encoding
  • 20.3. AML Byte Stream Byte Values
  • 20.4. AML Encoding of Names in the Namespace
• 21. ACPI Data Tables and Table Definition Language
  • 21.1. Types of ACPI Data Tables
  • 21.2. ACPI Table Definition Language Specification
    • 21.2.1. Overview of the Table Definition Language (TDL)
    • 21.2.2. TDL Grammar Specification
    • 21.2.3. Data Types
      • 21.2.3.1. Integers
      • 21.2.3.2. Integer Expressions
      • 21.2.3.3. Flags
      • 21.2.3.4. Strings
      • 21.2.3.5. Buffers
    • 21.2.4. Fields Set Automatically by the Compiler
    • 21.2.5. Special Fields
    • 21.2.6. TDL Generic Data Types
    • 21.2.7. Defining a Known ACPI Table in TDL
    • 21.2.8. Defining an Unknown or New ACPI table in TDL
    • 21.2.9. Table Definition Language Examples
      • 21.2.9.1. ECDT Disassembler Output
      • 21.2.9.2. ECDT Definition with Field Comments
    • 21.2.10. Minimal ECDT Definition
      • 21.2.10.1. Generic ACPI Table Definition

• A. Appendix A: Device Class Specifications
  • A.1. Overview
  • A.2. Device Power States
    • A.2.1. Bus Power Management
    • A.2.2. Display Power Management
    • A.2.3. PCMCIA/PCCARD/CardBus Power Management
    • A.2.4. PCI Power Management
    • A.2.5. USB Power Management
    • A.2.6. Device Classes
  • A.3. Default Device Class
    • A.3.1. Default Power Management Policy
    • A.3.2. Default Wake Events
    • A.3.3. Default Minimum Power Capabilities
  • A.4. Audio Device Class
    • A.4.1. Audio Device Power State Definitions
    • A.4.2. Audio Device Power Management Policy
    • A.4.3. Audio Device Wake Events
    • A.4.4. Audio Device Minimum Power Capabilities
  • A.5. COM Port Device Class
    • A.5.1. COM Port Power State Definitions
    • A.5.2. COM Power Power Management Policy
    • A.5.3. COM Port Wake Events
    • A.5.4. COM Port Minimum Power Capabilities
  • A.6. Display Device Class
    • A.6.1. Display Device Power State Definitions
      • A.6.1.1. Display Codecs
    • A.6.2. Display Device Power Management Policy
    • A.6.3. Display Device Wake Events
    • A.6.4. Display Device Minimum Power Capabilities
    • A.6.5. Display Device Performance States
      • A.6.5.1. Common Requirements for Display Class Performance States
      • A.6.5.2. Performance states for Full Screen Displays
      • A.6.5.3. Performance States for Video Controllers/Display Adapters
  • A.7. Input Device Class
    • A.7.1. Input Device Power State Definitions
    • A.7.2. Input Device Power Management Policy
    • A.7.3. Input Device Wake Events
    • A.7.4. Input Device Minimum Power Capabilities
  • A.8. Modem Device Class
    • A.8.1. Technology Overview
      • A.8.1.1. Traditional Connections
      • A.8.1.2. Power-Managed Connections
      • A.8.1.3. Motherboard Modems
    • A.8.2. Modem Device Power State Definitions
    • A.8.3. Modem Device Power Management Policy
    • A.8.4. Modem Device Wake Events
    • A.8.5. Modem Device Minimum Power Capabilities
  • A.9. Network Device Class
    • A.9.1. Network Device Power State Definitions
    • A.9.2. Network Device Power Management Policy
    • A.9.3. Network Device Wake Events
      • A.9.3.1. Link Status Events
      • A.9.3.2. Wake Frame Events
    • A.9.4. Network Device Minimum Power Capabilities
  • A.10. PC Card Controller Device Class
    • A.10.1. PC Card Controller Device Power State Definitions
    • A.10.2. PC Card Controller Device Power Management Policy
    • A.10.3. PC Card Controller Wake Events
    • A.10.4. PC Card Controller Minimum Power Capabilities
  • A.11. Storage Device Class
    • A.11.1. Storage Device Power State Definitions
    • A.11.2. Storage Device Power Management Policy
    • A.11.3. Storage Device Wake Events
    • A.11.4. Storage Device Minimum Power Capabilities
• B. Appendix B: Video Extensions
  • B.1. ACPI Extensions for Display Adapters: Introduction
  • B.2. Video Extension Definitions
  • B.3. ACPI Namespace
  • B.4. Display-specific Methods
    • B.4.1. _DOS (Enable/Disable Output Switching)
    • B.4.2. _DOD (Enumerate All Devices Attached to the Display Adapter)
    • B.4.3. _ROM (Get ROM Data)
    • B.4.4. _GPD (Get POST Device)
    • B.4.5. _SPD (Set POST Device)
    • B.4.6. _VPO (Video POST Options)
  • B.5. Notifications for Display Devices
  • B.6. Output Device-specific Methods
    • B.6.1. _ADR (Return the Unique ID for this Device)
    • B.6.2. _BCL (Query List of Brightness Control Levels Supported)
    • B.6.3. _BCM (Set the Brightness Level)
    • B.6.4. _BQC (Brightness Query Current level)
    • B.6.5. _DDC (Return the EDID for this Device)
    • B.6.6. _DCS (Return the Status of Output Device)
    • B.6.7. _DGS (Query Graphics State)
    • B.6.8. _DSS (Device Set State)
  • B.7. Notifications Specific to Output Devices
  • B.8. Notes on State Changes
• C. Appendix C: Deprecated Content