ACPI Specification

6.4 A

List of Tables
List of Figures
Revision History
Overview

1. Introduction
2. Definition of Terms
3. ACPI Concepts
4. ACPI Hardware Specification
5. ACPI Software Programming Model
6. Device Configuration
7. Power and Performance Management
8. Processor Configuration and Control
9. ACPI-Defined Devices and Device-Specific Objects
10. Power Source and Power Meter Devices
11. Thermal Management
12. ACPI Embedded Controller Interface Specification
13. ACPI System Management Bus Interface Specification
14. Platform Communications Channel (PCC)
15. System Address Map Interfaces
16. Waking and Sleeping
17. Non-Uniform Memory Access (NUMA) Architecture Platforms
18. ACPI Platform Error Interfaces (APEI)
19. ACPI Source Language (ASL) Reference
20. ACPI Machine Language (AML) Specification
21. ACPI Data Tables and Table Definition Language

A. Appendix A: Device Class Specifications
B. Appendix B: Video Extensions
C. Appendix C: Deprecated Content

Index

ACPI Specification

Docs »
List of Tables

List of Tables¶

Table 1.1 Hardware Type vs. OS Type Interaction

Table 2.1 Summary of Global Power States
Table 2.2 Summary of Device Power States

Table 3.1 Low Battery Levels
Table 3.3 Implementable Platform Types

Table 4.1 Feature-Programming Model Summary
Table 4.2 PM1 Event Registers
Table 4.3 PM1 Control Registers
Table 4.4 PM2 Control Register
Table 4.5 PM Timer Register
Table 4.6 Processor Control Registers
Table 4.7 General-Purpose Event Registers
Table 4.8 Power Button Support
Table 4.9 Sleep Button Support
Table 4.10 Alarm Field Decodings within the FADT
Table 4.11 PM1 Status Registers Fixed Hardware Feature Status Bits
Table 4.12 PM1 Enable Registers Fixed Hardware Feature Enable Bits
Table 4.13 PM1 Control Registers Fixed Hardware Feature Control Bits
Table 4.14 PM Timer Bits
Table 4.15 PM2 Control Register Bits
Table 4.16 Processor Control Register Bits
Table 4.17 Processor LVL2 Register Bits
Table 4.18 Processor LVL3 Register Bits
Table 4.19 Sleep Control Register
Table 4.20 Sleep Status Register

Table 5.1 Generic Address Structure (GAS)
Table 5.2 Address Space Format
Table 5.3 RSDP Structure
Table 5.4 DESCRIPTION_HEADER Fields
Table 5.5 DESCRIPTION_HEADER Signatures for tables defined by ACPI
Table 5.6 DESCRIPTION_HEADER Signatures for tables reserved by ACPI
Table 5.7 Root System Description Table Fields (RSDT)
Table 5.8 Extended System Description Table Fields (XSDT)
Table 5.9 FADT Format
Table 5.10 Fixed ACPI Description Table Fixed Feature Flags
Table 5.11 Fixed ACPI Description Table Boot IA-PC Boot
Table 5.12 Fixed ACPI Description Table ARM Boot Architecture Flags
Table 5.13 Firmware ACPI Control Structure (FACS)
Table 5.14 Firmware Control Structure Feature Flags
Table 5.15 OSPM Enabled Firmware Control Structure Feature Flags
Table 5.16 Global Lock Structure within the FACS
Table 5.17 Differentiated System Description Table Fields (DSDT)
Table 5.18 Secondary System Description Table Fields (SSDT)
Table 5.19 Multiple APIC Description Table (MADT) Format
Table 5.20 Multiple APIC Flags
Table 5.21 Interrupt Controller Structure Types
Table 5.22 Processor Local APIC Structure
Table 5.23 Local APIC Flags
Table 5.24 I/O APIC Structure
Table 5.25 Interrupt Source Override Structure
Table 5.26 MPS INTI Flags
Table 5.27 NMI Source Structure
Table 5.28 Local APIC NMI Structure
Table 5.29 Local APIC Address Override Structure
Table 5.30 I/O SAPIC Structure
Table 5.31 Processor Local SAPIC Structure
Table 5.32 Platform Interrupt Source Structure
Table 5.33 Platform Interrupt Source Flags
Table 5.34 Processor Local x2APIC Structure
Table 5.35 Local x2APIC NMI Structure
Table 5.36 GICC Structure
Table 5.37 GICC CPU Interface Flags
Table 5.38 GICD Structure
Table 5.39 GIC MSI Frame Structure
Table 5.40 GIC MSI Frame Flags
Table 5.41 GICR Structure
Table 5.42 GIC ITS Structure
Table 5.43 Multiprocessor Wakeup Structure
Table 5.44 Multiprocessor Wakeup Mailbox Structure
Table 5.45 Smart Battery Description Table (SBST) Format
Table 5.46 Embedded Controller Boot Resources Table Format
Table 5.47 Static Resource Affinity Table Format
Table 5.48 Processor Local APIC/SAPIC Affinity Structure
Table 5.49 Flags - Processor Local APIC/SAPIC Affinity Structure
Table 5.50 Memory Affinity Structure
Table 5.51 Flags - Memory Affinity Structure
Table 5.52 Processor Local x2APIC Affinity Structure
Table 5.53 GICC Affinity Structure
Table 5.54 Flags - GICC Affinity Structure
Table 5.55 Architecture Specific Affinity Structure
Table 5.56 Generic Initiator Affinity Structure
Table 5.57 Device Handle - ACPI
Table 5.58 Device Handle - PCI
Table 5.59 Flags - Generic Initiator Affinity Structure
Table 5.60 SLIT Format
Table 5.61 Corrected Platform Error Polling Table Format
Table 5.62 Corrected Platform Error Polling Processor Structure
Table 5.63 Maximum System Characteristics Table (MSCT) Format
Table 5.64 Maximum Proximity Domain Information Structure
Table 5.65 RASF Table format
Table 5.66 RASF Platform Communication Channel Shared Memory Region
Table 5.67 PCC Command Codes used by RASF Platform Communication Channel
Table 5.68 Platform RAS Capabilities Bitmap
Table 5.69 Parameter Block Structure for PATROL_SCRUB
Table 5.70 MPST Table Structure
Table 5.71 PCC Command Codes used by MPST Platform Communication Channel
Table 5.72 MPST Platform Communication Channel Shared Memory Region
Table 5.73 Power State Values
Table 5.74 Command Status
Table 5.75 Memory Power Node Structure definition
Table 5.76 Flag format
Table 5.77 Memory Power State Structure definition
Table 5.78 Memory Power State Characteristics Structure
Table 5.79 Flag format of Memory Power State Characteristics Structure
Table 5.80 Platform Memory Topology Table
Table 5.81 Common Memory Device
Table 5.82 Socket Type Data
Table 5.83 Memory Controller Type Data
Table 5.84 DIMM Type Specific Data
Table 5.85 Vendor Specific Type Data
Table 5.86 Boot Graphics Resource Table Fields
Table 5.87 Firmware Performance Data Table (FPDT) Format
Table 5.88 Performance Record Structure
Table 5.89 FPDT Performance Record Types
Table 5.90 Runtime Performance Record Types
Table 5.91 Firmware Basic Boot Performance Table Pointer Record
Table 5.92 S3 Performance Table Pointer Record
Table 5.93 Firmware Basic Boot Performance Table Header
Table 5.94 Firmware Basic Boot Performance Data Record
Table 5.95 S3 Performance Table Header
Table 5.96 Basic S3 Resume Performance Record
Table 5.97 Basic S3 Suspend Performance Record
Table 5.98 GTDT Table Structure
Table 5.99 Flag Definitions: Secure EL1 Timer, Non-Secure EL1 Timer, EL2 Timer, Virtual EL1 Timer and Virtual EL2 Timer
Table 5.100 Platform Timer Type Structures
Table 5.101 GT Block Structure Format
Table 5.102 GT Block Timer Structure Format
Table 5.103 Flag Definitions: GT Block Physical Timers and Virtual Timers
Table 5.104 Flag Definitions - Common Flags
Table 5.105 Arm Generic Watchdog Structure Format
Table 5.106 Flag Definitions - Arm Generic Watchdog Timer
Table 5.107 NVDIMM Firmware Interface Table (NFIT)
Table 5.108 NFIT Structure Types
Table 5.109 SPA Range Structure
Table 5.110 NVDIMM Region Mapping Structure
Table 5.111 Interleave Structure Index and Interleave Ways definition
Table 5.112 Interleave Structure
Table 5.113 SMBIOS Management Information Structure
Table 5.114 NVDIMM Control Region Structure Mark
Table 5.115 NVDIMM Block Data Windows Region Structure
Table 5.116 Flush Hint Address Structure
Table 5.117 Platform Capabilities Structure
Table 5.118 SDEV ACPI Table
Table 5.119 Secure Device Structures
Table 5.120 ACPI_NAMESPACE_DEVICE based Secure Device Structure
Table 5.121 Secure Access Component Types
Table 5.122 Identification Based Secure Access Component
Table 5.123 Memory-based Secure Access Component
Table 5.124 PCIe Endpoint Device-based Device Structure
Table 5.125 PCIe Endpoint Device-based Device Structure Example
Table 5.126 Heterogeneous Memory Attribute Table Header
Table 5.127 HMAT Structure Types
Table 5.128 Memory Proximity Domain Attributes Structure
Table 5.129 System Locality Latency and Bandwidth Information Structure
Table 5.130 Memory Side Cache Information Structure
Table 5.131 PDTT Structure
Table 5.132 PDTT Platform Communication Channel Identifier Structure
Table 5.133, Type 5 Platform Communication Channel Shared Memory
Table 5.134 PCC Commands Codes used by Platform Debug Trigger Table
Table 5.135 PDTT Platform Communication Channel
Table 5.136 Example: Platform with 4 debug triggers
Table 5.137 Processor Properties Topology Table
Table 5.138 Processor Hierarchy Node Structure
Table 5.139 Processor Structure Flags
Table 5.140 Cache Type Structure
Table 5.141 Cache Structure Flags
Table 5.142 Platform Health Assessment Table (PHAT) Format
Table 5.143 Platform Health Assessment Record Format
Table 5.144 Platform Health Assessment Record Type Format
Table 5.145 PHAT Version Element
Table 5.146 Firmware Version Data Record
Table 5.147 Firmware Health Data Record Structure
Table 5.148 Namespaces Defined Under the Namespace Root
Table 5.149 Operation Region Address Space Identifiers
Table 5.150 IPMI Status Codes
Table 5.151 Accsessor Type Values
Table 5.152 ACPI Event Programming Model Components
Table 5.153 Fixed ACPI Events
Table 5.154 Device Object Notification Values
Table 5.155 System Bus Notification Values
Table 5.156 Control Method Battery Device Notification Values
Table 5.157 Power Source Object Notification Values
Table 5.158 Thermal Zone Object Notification Values
Table 5.159 Control Method Power Button Notification Values
Table 5.160 Control Method Sleep Button Notification Values
Table 5.161 Control Method Lid Notification Values
Table 5.162 NVDIMM Root Device Notification Values
Table 5.163 NVDIMM Device Notification Values
Table 5.164 Processor Device Notification Values
Table 5.165 User Presence Device Notification Values
Table 5.166 Ambient Light Sensor Device Notification Values
Table 5.167 Power Meter Object Notification Values
Table 5.168 Processor Aggregator Device Notification Values
Table 5.169 Error Device Notification Values
Table 5.170 Fan Device Notification Values
Table 5.171 Memory Device Notification Values
Table 5.172 ACPI Device IDs
Table 5.173 Predefined ACPI Names
Table 5.174 Predefined Object Names
Table 5.175 Predefined Operating System Vendor String Prefixes
Table 5.176 Standard ACPI-Defined Feature Group Strings
Table 5.177 DeviceLockInfo Package Values

Table 6.1 Device Identification Objects
Table 6.2 ADR Object Address Encodings
Table 6.3 Additional Language ID Alias Strings
Table 6.4 _PLD Buffer 0 Return Value
Table 6.5 PLD Back Panel Example Settings
Table 6.6 Device Configuration Objects
Table 6.7 HPP Package Contents
Table 6.8 PCI Setting Record Content
Table 6.9 PCI-X Setting Record Content
Table 6.10 PCI Express Setting Record Content
Table 6.11 PCI Express Descriptor Setting Record Content
Table 6.12 PCI Express Register Descriptor
Table 6.13 Platform-Wide _OSC Capabilities DWORD 2
Table 6.14 OSPM USB Support Field
Table 6.15 OSPM USB Control Field
Table 6.16 Mapping Fields
Table 6.17 Example Relative Distances Between Proximity Domains
Table 6.18 Example System Locality Information Table
Table 6.19 Example Relative Distances Between Proximity Domains - 5 Node
Table 6.20 Device Insertion, Removal, and Status Objects
Table 6.21 OST Source Event Codes
Table 6.22 General Processing Status Codes
Table 6.23 Operating System Shutdown Processing (Source Events : 0x100) Status Codes
Table 6.24 Ejection Request / Ejection Processing (Source Events: 0x03 and 0x103) Status Codes
Table 6.25 Insertion Processing (Source Event: 0x200) Status Codes
Table 6.26 Small Resource Data Type Tag Bit Definitions
Table 6.27 Small Resource Items
Table 6.28 IRQ Descriptor Definition
Table 6.29 DMA Descriptor Definition
Table 6.30 Start Dependent Functions Descriptor Definition
Table 6.31 Start Dependent Function Priority Byte Definition
Table 6.32 End Dependent Functions Descriptor Definition
Table 6.33 I/O Port Descriptor Definition
Table 6.34 Fixed-Location I/O Port Descriptor Definition
Table 6.35 Fixed DMA Resource Descriptor
Table 6.36 Vendor-Defined Resource Descriptor Definition
Table 6.37 End Tag Definition
Table 6.38 Large Resource Data Type Tag Bit Definitions
Table 6.39 Large Resource Items
Table 6.40 24-bit Memory Range Descriptor Definition
Table 6.41 Large Vendor-Defined Resource Descriptor Definition
Table 6.42 32-Bit Memory Range Descriptor Definition
Table 6.43 32-bit Fixed-Location Memory Range Descriptor Definition
Table 6.44 Valid Combination of Address Space Descriptor Fields
Table 6.45 WORD Address Space Descriptor Definition
Table 6.46 DWORD Address Space Descriptor Definition
Table 6.47 WORD Address Space Descriptor Definition
Table 6.48 Extended Address Space Descriptor Definition
Table 6.49 Memory Resource Flag (Resource Type = 0) Definitions
Table 6.50 I/O Resource Flag (Resource Type = 1) Definitions
Table 6.51 Bus Number Range Resource Flag (Resource Type = 2) Definitions
Table 6.52 Extended Interrupt Descriptor Definition
Table 6.53 Generic Register Descriptor Definition
Table 6.54 GPIO Connection Descriptor Definition
Table 6.55 GenericSerialBus Connection Descriptors
Table 6.56 I2C Serial Bus Connection Descriptor
Table 6.57 SPI Serial Bus Connection Descriptor
Table 6.58 UART Serial Bus Connection Descriptor
Table 6.59 CSI-2 Connection Resource Descriptor
Table 6.60 Pin Function Description Definition
Table 6.61 Pin Configuration Descriptor Definition
Table 6.62 Pin Group Descriptor Definition
Table 6.63 Pin Group Function Descriptor Definition
Table 6.64 Pin Group Configuration Descriptor Description
Table 6.65 Other Objects and Methods
Table 6.66 OSPM _INI Object Actions
Table 6.67 NVDIMM Label Methods
Table 6.68 _LSI Return Package Values
Table 6.69 _LSR Return Package Values
Table 6.70, _CBR Return Package Values

Table 7.1 Power Resource Object Provisions for Information and Control
Table 7.2 Power Resource Methods
Table 7.3 Device Power Management Child Objects
Table 7.4 PSC Device State Codes
Table 7.5 Power Resource Requirements Package
Table 7.6 S1 Action / Result Table
Table 7.7 S2 Action / Result Table
Table 7.8 S3 Action / Result Table
Table 7.9 S4 Action / Result Table
Table 7.10 BIOS-Supplied Control Methods for System-Level Functions
Table 7.11 System State Package

Table 8.1 C-state/T-state/P-state Coordination Types
Table 8.2 Cstate Package Values
Table 8.3 C-State Dependency Package Values
Table 8.4 Processor Container Device Objects
Table 8.5 Valid Local State Combinations in preceding example system
Table 8.6 OS Initiated Flow
Table 8.7 Example of incorrect platform state in OS Initiated Request without Dependency Check
Table 8.8 OS Initiated Request Semantics with Dependency Check
Table 8.9 Example of incorrect platform state in OS Initiated Request without Hierarchy Parameter
Table 8.10 OS Initiated Request Semantics with Hierarchy Parameter
Table 8.11 Local Power States for the Parent Processor or Processor Container
Table 8.12 Extended LPI Fields
Table 8.13 Flags for LPI states
Table 8.14 Enabled Parent State values for example system
Table 8.15 Entry method example
Table 8.16 _RDI package return values
Table 8.17 _PTC Package Values
Table 8.18 TState Package Values
Table 8.19 T-State Dependency Package Values
Table 8.20 _PCT Package Values
Table 8.21 PState Package Values
Table 8.22 P-State Dependency Package Values
Table 8.23 Continuous Performance Control Package Values
Table 8.24 Performance Limited Register Status Bits
Table 8.25 PCC Command Codes Used by Collaborative Processor Performance Control
Table 8.26 Processor Aggregator Device Objects

Table 9.1 System Indicator Control Methods
Table 9.2 Control Method Ambient Light Sensor Device
Table 9.3 Control Method Lid Device
Table 9.4 ATA Specific Objects
Table 9.5 GTM Method Result Codes
Table 9.6 Tape Presence
Table 9.7 ACPI Floppy Drive Information
Table 9.8 MBM Package Details
Table 9.9 MSM Result Encoding
Table 9.10 Memory Device _OSC Capabilities DWORD number 2
Table 9.11 UPC Return Package Values
Table 9.12 User Presence Detection Device
Table 9.13 Time and Alarm Device
Table 9.14 Generic Buttons Device Child Objects
Table 9.15 Usage Types and Interrupt Polarity
Table 9.16 Common HID Button Usages
Table 9.17 NVDIMM Root Device Function Index
Table 9.18 Status and Extended Status Field Generic Interpretations
Table 9.19 Query ARS Capabilities - Input Buffer
Table 9.20 Query ARS Capabilities - Output Buffer
Table 9.21 Start ARS - Input Buffer
Table 9.22 Start ARS - Output Buffer
Table 9.23 Query ARS Status - Output Buffer
Table 9.24 ARS Data
Table 9.25 ARS Error Record Format
Table 9.26 Clear Uncorrectable Error - Input Buffer
Table 9.27 Clear Uncorrectable Error - Output Buffer
Table 9.28 Translate SPA - Input Payload Format
Table 9.29 Translate SPA - Output Payload Format
Table 9.30 Translate SPA - Translated NVDIMM Device List Output Payload Format
Table 9.31 ARS Error Inject - Input Format
Table 9.32 ARS Error Inject - Output Format
Table 9.33 ARS Error Inject Clear - Input Format
Table 9.34 ARS Error Inject Clear - Output Format
Table 9.35 ARS Error Inject Status Query - Output Format
Table 9.36 ARS Error Inject Status Query - Error Record Format
Table 9.37 ARS Error Inject Options Support
Table 9.38 NVDIMM Device Method Return Status Code
Table 9.39 NCH Return Value
Table 9.40 _NBS Return Value
Table 9.41 _NIC Output Buffer
Table 9.42 _NIH Input Buffer
Table 9.43 _NIH Output Buffer
Table 9.44 _NIG Output Buffer

Table 10.1 Example SMBus Device Slave Addresses
Table 10.2 Smart Battery Objects
Table 10.3 Battery Control Methods
Table 10.4 BIF Return Package Values
Table 10.5 BIX Return Package Values
Table 10.6 BMD Return Package Values
Table 10.7 _BPC Return Package Values
Table 10.8 Battery Power Threshold Support Capability
Table 10.9 _BPS Return Package Values
Table 10.10 BST Return Package Values
Table 10.11 Control Method Battery _OSC Capabilities DWORD2 Bit Definitions
Table 10.12 Power Source Objects
Table 10.13 PIF Method Result Codes
Table 10.14 Power Meter Objects
Table 10.15 PMC Method Result Codes
Table 10.16 Wireless Power Calibration
Table 10.17 Wireless Power Control Notification Values

Table 11.1 Fan Specific Objects
Table 11.2 FIF Package Details
Table 11.3 FPS FanPstate Package Details
Table 11.4 FST Package Details
Table 11.5 Thermal Objects
Table 11.6 Thermal Relationship Package Values 1
Table 11.7 Thermal Relationship Package Values 2

Table 12.1 Read Only Register Table
Table 12.2 Embedded Controller Commands
Table 12.3 Events for Which Embedded Controller Must Generate SCIs
Table 12.4 Read Command (3 Bytes)
Table 12.5 Write Command (3 Bytes)
Table 12.6 Query Command (2 Bytes)
Table 12.7 Burst Enable Command (2 Bytes)
Table 12.8 Burst Disable Command (1 Byte)
Table 12.9 Status Register, SMB_STS
Table 12.10 SMBus Status Codes
Table 12.11 Protocol Register, SMB_PRTCL
Table 12.12 Address Register, SMB_ADDR
Table 12.13 Command Register, SMB_CMD
Table 12.14 Data Register Array, SMB_DATA[i], i=0-31
Table 12.15 Block Count Register, SMB_BCNT
Table 12.16 Alarm Address Register, SMB_ALRM_ADDR
Table 12.17 Alarm Data Registers, SMB_ALRM_DATA[0], SMB_ALRM_DATA[1]
Table 12.18 SMB EC Interface
Table 12.19 Embedded Controller Device Object Control Methods
Table 12.20 EC SMBus HC Device Objects

Table 13.1 SMBus Protocol Types

Table 14.1 Platform Communications Channel Table (PCCT)
Table 14.2 Platform Communications Channel Global Flags
Table 14.3 Generic PCC Subspace Structure
Table 14.4 PCC Subspace Structure type 0 (Generic Communications Subspace)
Table 14.5 PCC Subspace Structure type 1 (HW-Reduced Communications Subspace)
Table 14.6 PCC Subspace Structure type 2 (HW-Reduced Communications Subspace)
Table 14.7 PCC Subspace Structure type 3 and type 4
Table 14.8 HW Registers based Communications Subspace Structure (Type 5)
Table 14.9 Generic Communications Channel Shared Memory Region
Table 14.10 Generic Communications Channel Command Field
Table 14.11 Generic Communications Channel Status Field
Table 14.12 Initiator Responder Communications Channel Shared Memory Region
Table 14.13 Initiator Responder Communications Channel Flags
Table 14.14 Reduced PCC Subspace Shared Memory Region

Table 15.1 Address Range Types
Table 15.2 Input to the INT 15h E820h Call
Table 15.3 Output from the INT 15h E820h Call
Table 15.4 Address Range Descriptor Structure
Table 15.5 Extended Attributes for Address Range Descriptor Structure
Table 15.6 UEFI Memory Types and mapping to ACPI address range types
Table 15.7 Sample Memory Map

Table 18.1 Boot Error Record Table (BERT)
Table 18.2 Hardware Error Source Table (HEST)
Table 18.3 IA-32 Architecture Machine Check Exception Structure
Table 18.4 IA-32 Architecture Machine Check Error Bank Structure
Table 18.5 IA-32 Architecture Corrected Machine Check Structure
Table 18.6 IA-32 Architecture NMI Error Structure
Table 18.7 PCI Express Root Port AER Structure
Table 18.8 PCI Express Device AER Structure
Table 18.9 PCI Express/PCI-X Bridge AER Structure
Table 18.10 Generic Hardware Error Source Structure
Table 18.11 Generic Error Status Block
Table 18.12 Generic Error Data Entry
Table 18.13 Generic Hardware Error Source version 2 (GHESv2) Structure
Table 18.14 Hardware Error Notification Structure
Table 18.15 IA-32 Architecture Deferred Machine Check Structure
Table 18.16 Error Record Serialization Table (ERST)
Table 18.17 Error Record Serialization Actions
Table 18.18 Command Status Definition
Table 18.19 Serialization Instruction Entry
Table 18.20 Serialization Instructions
Table 18.21 Instruction Flags
Table 18.22 Error Record Serialization Info
Table 18.23 Error Injection Table (EINJ)
Table 18.24 Error Injection Actions
Table 18.25 Injection Instruction Entry
Table 18.26 Instruction Flags
Table 18.27 Injection Instructions
Table 18.28 Command Status Definition
Table 18.29 Error Type Definition
Table 18.30 SET_ERROR_TYPE_WITH_ADDRESS Data Structure
Table 18.31 Vendor Error Type Extension Structure
Table 18.32 Trigger Error Action

Table 19.1 ASL Grammar Notation
Table 19.2 Named Object Reference Encodings
Table 19.3 Definition Block Name Modifier Encodings
Table 19.4 ASL Escape Sequences
Table 19.5 Summary of ASL Data Types
Table 19.6 Data Types and Type Conversions
Table 19.7 Object Conversion Rules
Table 19.8 Object Storing and Copying Rules
Table 19.9 Reading from ArgX Objects
Table 19.10 Writing to ArgX Objects
Table 19.11 Reading from LocalX Objects
Table 19.12 Writing to LocalX Objects
Table 19.13 Reading from Named Objects
Table 19.14 Writing to Named Objects
Table 19.15 ASL Operators Summary List
Table 19.16 ASL compiler controls
Table 19.17 ACPI table management
Table 19.18 Miscellaneous named object creation
Table 19.19 Operation Regions and Fields
Table 19.20 Buffer Fields
Table 19.21 Synchronization
Table 19.22 Object references
Table 19.23 Integer arithmetic
Table 19.24 Logical operators
Table 19.25 Method execution control
Table 19.26 Data type conversion and manipulation
Table 19.27 Resource Descriptor macros
Table 19.28 Constants
Table 19.29 Control method objects
Table 19.30 Concatenate Data Types
Table 19.31 Concatenate Object Types
Table 19.32 Debug Object Display Formats
Table 19.33 Field Unit List Entries
Table 19.34 OperationRegion Address Spaces and Access Types
Table 19.35 Match Term Operator Meanings
Table 19.36 Values Returned By the ObjectType Operator
Table 19.37 Pin Configuration Types and Values
Table 19.38 Pin Group Configuration Types and Values
Table 19.39 PLD Keywords and Assignment Types
Table 19.40 PLD Keywords and assignable String Values
Table 19.41 UUID Buffer Format
Table 19.42 UART Serial Bus Connection Resource Descriptor - Version 2 Macro

Table 20.1 AML Grammar Notation Conventions
Table 20.2 AML Byte Stream Byte Values

Table A-1: Default Power State Definitions
Table A-2: Default Power Management Policy
Table A-3: Audio Device Power State Definitions
Table A-4: Audio Device Power Management Policy
Table A-5: COM Port Device Power State Definitions
Table A-6: COM Port Device Power Management Policy
Table A-7: CRT Monitors Power State Definitions
Table A-8: Internal Flat Panel Displays Power State Definitions
Table A-9: External Digital Displays Power State Definitions
Table A-10: Standard TV Devices and Analog HDTVs Power State Definitions
Table A-11: Other (new) Full Screen Display Devices Power State Definitions
Table A-12: Video Controllers (Graphics Adapters) Power State Definitions
Table A-13: Display Device Power Management Policy
Table A-14: Input Device Power State Definitions
Table A-15: Input Device Power Management Policy
Table A-16: Modem Device Power State Definitions
Table A-17: Modem Device Power Management Policy
Table A-18: Network Device Power State Definitions
Table A-19: Network Device Power Management Policy
Table A-20: PC Card Controller Power State Definitions
Table A-21: PC Card Controller Power Management Policy
Table A-22: Hard Disk, CD-ROM and IDE/ATAPI Removable Storage Devices Power State Definitions
Table A-23: Floppy Disk Devices Power State Definitions
Table A-24: IDE Channel Devices Power State Definitions
Table A-25: Hard Disk, Floppy Disk, CD-ROM and IDE/ATAPI Removable Storage Devices Power Management Policy
Table A-26: IDE Channel Devices Power Management Policy

Table B-1: Video Extension Object Requirements
Table B-2: Video Output Device Attributes
Table B-3: Example Device IDs
Table B-4: Notifications for Display Devices
Table B-5: Output Device Status
Table B-6: Device State for _DGS
Table B-7: Device State for _DSS
Table B-8: Notification Values for Output Devices

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