List of Tables
Chapter 1
Chapter 2
Table 2.5 Map EFI Cacheability Attributes to AArch64 Memory Types
Table 2.6 Map UEFI Permission Attributes to ARM Paging Attributes
Chapter 3
Chapter 4
Chapter 5
Table 5.4 Protective MBR Partition Record protecting the entire disk*
Table 5.7 Defined GPT Partition Entry — Partition Type GUIDs
Chapter 6
Chapter 7
Chapter 8
Chapter 9
Chapter 10
Chapter 11
Chapter 12
Chapter 13
Chapter 14
Table 14.5 PCI Root Bridge Device Path for Bridge #0 in a Server System
Table 14.6 PCI Root Bridge Device Path for Bridge #1 in aServer System
Table 14.7 PCI Root Bridge Device Path for Bridge #2 in aServer System
Table 14.8 PCI Root Bridge Device Path for Bridge #3 in a Server System
Table 14.13 PCI Device 7, Function 0 behind PCI to PCI bridge
Table 14.14 Standard PCI Expansion ROM Header (Example from PCI Firmware Specification 3.0)
Table 14.15 PCI Expansion ROM Code Types (Example from PCI Firmware Specification 3.0)
Table 14.17 Device Path for an EFI Driver loaded from PCIO ption ROM
Chapter 15
Table 15.6 Single Channel PCI SCSI Controller Behind a PCI Bridge
Table 15.7 Channel #3 of a PCI SCSI Controller behind a PCIBridge
Chapter 16
Chapter 17
Chapter 18
Chapter 19
Chapter 20
Chapter 21
Chapter 22
Chapter 23
Chapter 24
Chapter 25
Chapter 26
Chapter 27
Chapter 28
Chapter 29
Chapter 30
Table 30.1 Descriptions of Parameters in MTFTPv4 PacketStructures
Table 30.2 Descriptions of Parameters in MTFTPv6 PacketStructures
Chapter 31
Chapter 32
Table 32.3 CHAP Authentication Node Structure using Local Database
Table 32.4 PE/COFF Certificates Types and UEFI Signature Database Certificate Types
Chapter 33
Table 33.3 Common Control Codes for Font Display Information
Table 33.6 Truth Table: Mapping A Single Question To Three Configuration Settings
Chapter 34
Chapter 35
Callback 36
Chapter 37
Appendix A
Appendix B
Table B.2 EFI Scan Codes for EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL
Table B.3 Control Sequences to Implement EFI_SIMPLE_TEXT_INPUT_PROTOCOL
Appendix C
Appendix D
Appendix E
Appendix F
Appendix G
Appendix H
Appendix I
Appendix J
Appendix K
Appendix L
Appendix M
Appendix N
Table N.21 ARM Processor Error Context Information HeaderStructure
Table N.23 ARM AArch32 EL1 Context System Registers (Type 1)
Table N.24 ARM AArch32 EL2 Context System Registers (Type 2)
Table N.25 ARM AArch32 secure Context System Registers (Type3)
Table N.27 ARM AArch64 EL1 Context System Registers (Type 5)
Table N.28 ARM AArch64 EL2 Context System Registers (Type 6)
Table N.29 ARM AArch64 EL3 Context System Registers (Type 7)
Table N.30 ARM Misc. Context System Register (Type 8) - SingleRegister Entry
Appendix O
Appendix P
Appendix Q
Appendix R