UEFI Platform Initialization Specification
Version 1.9
  • Specification Organization
  • Revision History
  • Volume I: Pre-EFI Initialization Core Interface
  • List of Figures
  • List of Tables
  • 1. Introduction
  • 2. Overview
  • 3. PEI Services Table
  • 4. Services - PEI
  • 5. PEI Foundation
  • 6. Architectural PPIs
  • 7. PEIMs
  • 8. Additional PPIs
  • 9. PEI to DXE Handoff
  • 10. Boot Paths
  • 11. PEI Physical Memory Usage
  • 12. Special Paths Unique to the Itanium® Processor Family
  • 13. Security (SEC) Phase Information
  • 14. Dependency Expression Grammar
  • 15. TE Image
  • 16. TE Image Creation
  • 17. TE Image Loading
  • Volume II: Driver Execution Environment Core Interface
  • List of Figures
  • List of Tables
  • 1. Introduction
  • 2. Overview
  • 3. Boot Manager
  • 4. UEFI System Table
  • 5. Services - Boot Services
  • 6. Runtime Capabilities
  • 7. Services - DXE Services
  • 8. Protocols - Device Path Protocol
  • 9. DXE Foundation
  • 10. DXE Dispatcher
  • 11. DXE Drivers
  • 12. DXE Architectural Protocols
  • 13. DXE Boot Services Protocol
  • 14. DXE Runtime Protocols
  • 15. Dependency Expression Grammar
  • Appendix: Error Codes
  • Appendix: GUID Definitions
  • Volume III: Shared Architectural Elements
  • List of Figures
  • List of Tables
  • 1. Introduction
  • 2. Firmware Storage Design Discussion
  • 3. Firmware Storage Code Definitions
  • 4. HOB Design Discussion
  • 5. HOB Code Definitions
  • 6. Status Codes
  • 7. Report Status Code Routers
  • 8. PCD
  • Volume IV: Management Mode Core Interface
  • List of Figures
  • List of Tables
  • 1. Overview
  • 2. MM Foundation Entry Point
  • 3. Management Mode System Table (MMST)
  • 4. MM Protocols
  • 5. UEFI Protocols
  • 6. PI PEI PPIs
  • 7. MM Child Dispatch Protocols
  • 8. Interactions with PEI, DXE, and BDS
  • 9. Other Related Notes For Support Of MM Drivers
  • 10. MCA/INIT/PMI Protocol
  • 11. Extended SAL Services
  • 12. SMM SPI Protocol Stack
  • Appendix: Management Mode Backward Compatibility Types
  • Volume V: Standards
  • List of Figures
  • List of Tables
  • 1. Introduction
  • 2. SMBus Host Controller Design Discussion
  • 3. SMBus Host Controller Code Definitions
  • 4. SMBus Design Discussion
  • 5. SMBus PPI Code Definitions
  • 6. SMBIOS Protocol
  • 7. IDE Controller
  • 8. S3 Resume
  • 9. ACPI System Description Table Protocol
  • 10. PCI Host Bridge
  • 11. PCI Platform
  • 12. Hot Plug PCI
  • 13. Super I/O Protocol
  • 14. Super I/O and ISA Host Controller Interactions
  • 15. CPU I/O Protocol
  • 16. Legacy Region Protocol
  • 17. I2C Protocol Stack
  • 18. SPI Protocol Stack
  • Appendix: Error Codes
Index
UEFI Platform Initialization Specification
  • List of Tables

List of Tables

  • Drivers Involved in Configuring IDE Devices

  • Field descriptiond forEFI_IDE_CONTROLLER_ENUM_PHASE

  • EFI_ATAPI_IDENTIFY_DATA Definition .

  • Functions in Legacy Region Protocol

  • Standard PCI Devices - Header Type 0

  • PCI-to-PCI Bridge - Header Type 1

  • ACPI 2.0 & 3.0 QWORD Address Space Descriptor Usage

  • ACPI 2.0 & 3.0 End Tag Usage

  • I/O Resource Flag (Resource Type = 1) Usage

  • Memory Resource Flag (Resource Type = 0) Usage

  • Enumeration Descriptions

  • EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTESfield descriptions

  • ACPI 2.0 & 3.0 Resource Descriptor FieldValues for StartBusEnumeration()

  • ACPI 2.0 & 3.0 Resource Descriptor FieldValues for SetBusNumbers()

  • ACPI 2.0& 3.0 Resource Descriptor FieldValues for SubmitResources()

  • ACPI 2.0 & 3.0 GetProposedResources()Resource Descriptor Field Values

  • EFI_RESOURCE_ALLOCATION_STATUS fielddescriptions

  • EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASEfield descriptions

  • Description of possible states for EFI_HPC_STATE

  • EFI_HPC_PADDING_ATTRIBUTES field descriptions

  • ACPI 2.0 & 3.0 QWORD Address Space Descriptor Usage

  • ACPI 2.0 & 3.0 End Tag Usage

  • Host Bus Controllers

  • Producing the PCI Host Bridge Resource Allocation Protocol

  • Desktop System with 1 PCI Root Bridge

  • Server System with 4 PCI Root Bridges

  • Server System with 2 PCI Segments

  • Server System with 2 PCI Host Buses

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