List of Figures

Fig. i-1 - ACPI overview
Fig. i-2 - ACPI Structure
Fig. i-3 - ASL and AML
Fig. i-4 ACPI Initialization
Fig. i-5 Runtime Thermal Event
Fig. 1.1 OSPM/ACPI Global System
Fig. 3.1 Global System Power States and Transitions
Fig. 3.2 Example Modem and COM Port Hardware
Fig. 3.3 Reporting Battery Capacity
Fig. 3.4 Formula for Remaining Battery Percentage
Fig. 3.5 Formula for the Present Drain Rate
Fig. 3.6 Low Battery and Warning
Fig. 4.1 Generic Hardware Feature Model
Fig. 4.2 Global States and Their Transitions
Fig. 4.3 Example Event Structure for a Legacy/ACPI Compatible Event Model
Fig. 4.4 Block Diagram of a Status/Enable Cell
Fig. 4.5 Example Fixed Hardware Feature Register Grouping
Fig. 4.6 Register Blocks versus Register Groupings
Fig. 4.7 Power Management Timer
Fig. 4.8 Fixed Power Button Logic
Fig. 4.9 Fixed Hardware Sleep Button Logic
Fig. 4.10 Sleeping/Wake Logic
Fig. 4.11 RTC Alarm
Fig. 4.12 Power Management Events to SMI/SCI Control Logic
Fig. 4.13 Example of General-Purpose vs. Generic Hardware Events
Fig. 4.14 Example Generic Address Space Lid Switch Logic
Fig. 5.1 Root System Description Pointer and Table
Fig. 5.2 Description Table Structures
Fig. 5.3 APIC-Global System Interrupts
Fig. 5.4 8259 - Global System Interrupts
Fig. 5.5 MPST ACPI Table Overview
Fig. 5.6 Memory Power State Transitions
Fig. 5.7 Image Offset
Fig. 5.8 FPDT Hierarchy Structure
Fig. 5.9 NVDIMM Firmware Interface Table (NFIT) Overview
Fig. 5.10 HMAT Representation
Fig. 5.11 Memory Side Cache Example
Fig. 5.12, Mapping a PDTT Debug Trigger Table Entry to a PCCT PCC Subspace
Fig. 5.13 Example: Platform with four debug triggers
Fig. 5.14 L1 Cache Structure
Fig. 5.15 Cache Type Structure - Type 1 Example
Fig. 5.16 Example ACPI NameSpace
Fig. 5.17 AML Encoding
Fig. 6.1 System Panel and Panel Origin Positions
Fig. 6.2 Laptop Panel and Panel Origin Positions
Fig. 6.3 Default Shape Definitions
Fig. 6.4 PLD Back Panel Rendering
Fig. 6.5 System Locality information Table
Fig. 6.6 Device Ejection Flow Example Using _OST
Fig. 7.1 Working / Sleeping State object evaluation flow
Fig. 8.1 Processor Power States
Fig. 8.2 Throttling Example
Fig. 8.3 Equation 1 Duty Cycle Equation
Fig. 8.4 Example Control for the STPCLK
Fig. 8.5 ACPI Clock Logic (One per Processor)
Fig. 8.6 Processor Hierarchy
Fig. 8.7 Power states for processor hierarchy
Fig. 8.8 Worst case wake latency
Fig. 8.9 Energy of states A,B and C versus sleep duration
Fig. 8.10 Platform performance thresholds
Fig. 8.11 OSPM performance controls
Fig. 9.1 A five-point ALS Response Curve
Fig. 9.2 A two-point ALS Response Curve
Fig. 9.3 Example Response Curve for a Transflective Display
Fig. 9.4 USB ports
Fig. 9.5 Persistence of expired timer events
Fig. 9.6 System transitions with WakeAlarm — Timer
Fig. 9.7 System transitions with WakeAlarm — Policy
Fig. 9.8 Vendor/Device Specific Driver Loading
Fig. 10.1 Typical Smart Battery Subsystem (SBS)
Fig. 10.2 Single Smart Battery Subsystem
Fig. 10.3 Smart Battery Subsystem
Fig. 10.4 Remaining Battery Percent Formula
Fig. 10.5 Remaining Battery Life Formula
Fig. 10.6 Power Meter and Power Source/Docking Namespace Example
Fig. 11.1 ACPI Thermal Zone
Fig. 11.2 Thermal Events
Fig. 11.3 Temperature and CPU Performance Versus Time
Fig. 11.4 Active and Passive Threshold Values
Fig. 11.5 Cooling Preferences
Fig. 12.1 Shared Interface
Fig. 12.2 Private Interface
Fig. 12.3 Interrupt Model
Fig. 13.1 Bit Encoding Example
Fig. 13.2 Smart Battery Subsystem Devices
Fig. 13.3 Smart Battery Device Virtual Registers
Fig. 14.1 Communication flow of the doorbell protocol
Fig. 14.2 Communication flow for notifications on Responder subspaces
Fig. 16.1 Example Sleeping States
Fig. 16.2 Platform Firmware Initialization
Fig. 16.3 Example Physical Memory Map
Fig. 16.4 Memory as Configured after Boot
Fig. 16.5 OS Initialization
Fig. 18.1 APEI error flow example with external RAS controller
Fig. B-1 Example Display Architecture